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NUS5530MN Datasheet(PDF) 1 Page - ON Semiconductor |
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NUS5530MN Datasheet(HTML) 1 Page - ON Semiconductor |
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1 / 9 page  © Semiconductor Components Industries, LLC, 2006 May, 2006 − Rev. 0 1 Publication Order Number: NUS5530MN/D NUS5530MN Integrated Power MOSFET with PNP Low VCE(sat) Switching Transistor This integrated device represents a new level of safety and board−space reduction by combining the 20 V P−Channel FET with a PNP Silicon Low VCE(sat) switching transistor. This newly integrated product provides higher efficiency and accuracy for battery powered portable electronics. Features • Low RDS(on) (MOSFET) and Low VCE(sat) (Transistor) • Higher Efficiency Extending Battery Life • Logic Level Gate Drive (MOSFET) • Performance DFN Package • This is a Pb−Free Device Applications • Power Management in Portable and Battery−Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards MAXIMUM RATINGS FOR P−CHANNEL FET (TA = 25°C unless otherwise noted) Rating Symbol 5 sec Steady State Unit Drain−Source Voltage VDS −20 V Gate−Source Voltage VGS "12 V Continuous Drain Current (TJ = 150°C) (Note 1) TA = 25°C TA = 85°C ID −5.3 −3.8 −3.9 −2.8 A Pulsed Drain Current IDM "20 A Continuous Source Current (Note 1) IS −5.3 −3.9 A Maximum Power Dissipation (Note 1) TA = 25°C TA = 85°C PD 2.5 1.3 1.3 0.7 W Operating Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). Device Package Shipping† ORDERING INFORMATION http://onsemi.com †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NUS5530MNR2G DFN8 (Pb−Free) 3000/Tape & Reel DFN8 CASE 506AL N/C Collector Source Drain Emitter Base N/C Gate (Bottom View) PIN ASSIGNMENT A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package 1 2 3 4 8 7 6 5 1 8 Collector Drain (Top View) 1 2 3 4 8 7 6 5 1 MARKING DIAGRAM 5530 AYWW G G (Note: Microdot may be in either location) |
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