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AD7367 Datasheet(PDF) 8 Page - Analog Devices

Part No. AD7367
Description  True Bipolar Input, Dual 1us, 14-Bit, 2-Channel SAR ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7367 Datasheet(HTML) 8 Page - Analog Devices

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AD7367
Preliminary Technical Data
Rev. PrD | Page 8 of 16
applied externally to the rest of a system.
10
VSS
Negative power supply voltage. This is the negative supply voltage for the Analog Input section. The supply
must be less than a maximum voltage of -11.5V for all input ranges. See Table 6 for further details. 10 µF and
100 nF decoupling capacitors should be placed on the VSS pin.
11,12
VA1, VA2
Analog Inputs of ADC A. These are both single-ended analog inputs. The Analog input range on these
channels is determined by the RANGE0 and RANGE1 pins.
13,14
VB2, VB1
Analog Inputs of ADC B. These are both single-ended analog inputs. The Analog input range on these
channels is determined by the RANGE0 and RANGE1 pins.
15
VDD
Positive power supply voltage. This is the positive supply voltage for the Analog Input section. The supply
must be greater than a minimum voltage of 11.5V for all the analog input ranges. See Table 6 for further
details. 10 µF and 100 nF decoupling capacitors should be placed on the VDD pin.
18
REFSEL
Internal/External Reference Selection. Logic input. If this pin is tied to a logic high, the on-chip 2.5 V
reference is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB
must be tied to decoupling capacitors. If the REF SELECT pin is tied to GND, an external reference can be
supplied to the AD7367 through the DCAPA and/or DCAPB pins.
19
CS
Chip Select. Active low logic input. This input frames the serial data transfer. When CS is logic low the
output bus is enabled and the conversion result is output on DOUTA, and DOUTB.
20
SCLK
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7367.
21
CONVST
Conversion Start. Edge triggered logic input. On the falling edge of this input the track/hold goes into hold
mode and conversion is initiated. If CONVST is low at the end of a conversion, the part goes into power-
down mode. In this case, the rising edge of CONVST will instruct the part to power up again.
22
BUSY
BUSY Output. Transitions high when a conversion is started and remains high until the conversion is
complete.
24
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7367. The DGND pin
should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the
same potential and must not be more than 0.3 V apart, even on a transient basis.


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