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AD7366 Datasheet(PDF) 8 Page - Analog Devices

Part No. AD7366
Description  True Bipolar Input, Dual 1us, 12-Bit, 2-Channel SAR ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7366 Datasheet(HTML) 8 Page - Analog Devices

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AD7366
Preliminary Technical Data
Rev. PrG | Page 8 of 17
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DOUTA 1
2
3
ADDR
4
DGND
24
23
BUSY
22
CNVST
21
RANGE0
5
RANGE1
6
AGND
7
SCLK
20
CS
19
REFSEL
18
8
AGND
17
9
16
10
15
11
14
12
13
AD7366
TOP VIEW
(Not to Scale)
DOUTB
DCAPADCAPB
DVCC
AVCC
VSS
VA1
VA2
VB1
VB2
VDD
VDRIVE
Figure 2 24-Lead RU-24.
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 23
DOUTA,
DOUTB
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input and 12 SCLK cycles are required to access the data. The data
simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream
consists of the 12 bits of conversion data and is provided MSB first. If CS is held low for a further 12 SCLK
cycles on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data
from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB
using only one serial port. See the Serial Interface section.
2
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will
operate. This pin should be decoupled to DGND. The voltage range on this pin is 2.7V to 5.25V and may be
different to that at AVCC and DVCC but should never exceed either by more than 0.3V. To achieve a
throughput rate of 1.12Msps VDRIVE must be greater than or equal to 4.75V
3
DVCC
Digital Supply Voltage, 4.75V to 5.25V. The DVCC and AVCC voltages should ideally be at the same potential.
For best performance it is recommended that DVCC and AVCC pins be shorted together, to ensure the voltage
difference between them never exceed 0.3 V even on a transient basis. This supply should be decoupled to
DGND. 10 µF and 100 nF decoupling capacitors should be placed on the DVCC pin.
4,5
RANGE0,
RANGE1
Analog Input Range Selection. Logic inputs. The polarity on these pins determines the input range of
the analog input channels. See Analog Inputs section and
Table 7 for details
6
ADDR
Multiplexer Select. Logic input. This input is used to select the pair of channels to be simultaneously
converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADCB. The logic
state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion.
7,17
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7366. All analog input signals and
any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and
must not be more than 0.3 V apart, even on a transient basis.
8
AVCC
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and DVCC
voltages ideally should be at the same potential. For best performance it is recommended that DVCC and
AVCC pins be shorted together, to ensure the voltage difference between them never exceed 0.3 V even on a
transient basis. This supply should be decoupled to AGND. 10 µF and 100 nF decoupling capacitors should


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