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AD7329 Datasheet(PDF) 17 Page - Analog Devices

Part No. AD7329
Description  1 MSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
Download  40 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7329 Datasheet(HTML) 17 Page - Analog Devices

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AD7329
Rev. 0 | Page 17 of 40
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7329 is a fast, 8-channel, 12-bit plus sign, bipolar input,
serial A/D converter. The AD7329 can accept bipolar input ranges
that include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to
+10 V unipolar input range. A different analog input range can
be programmed on each analog input channel via the on-chip
registers. The AD7329 has a high speed serial interface that can
operate at throughput rates up to 1 MSPS.
The AD7329 requires VDD and VSS dual supplies for the high
voltage analog input structures. These supplies must be equal to
or greater than the analog input range. See Table 6 for the
requirements of these supplies for each analog input range. The
AD7329 requires a low voltage 2.7 V to 5.25 V VCC supply to
power the ADC core.
Table 6. Reference and Supply Requirements for Each
Analog Input Range
Selected
Analog
Input
Range (V)
Reference
Voltage (V)
Full-Scale
Input
Range (V)
AVCC (V)
Minimum
VDD/VSS (V)
±10
2.5
±10
3/5
±10
3.0
±12
3/5
±12
±5
2.5
±5
3/5
±5
3.0
±6
3/5
±6
±2.5
2.5
±2.5
3/5
±5
3.0
±3
3/5
±5
0 to +10
2.5
0 to +10
3/5
+10/AGND
3.0
0 to +12
3/5
+12/AGND
In order to meet the specified performance specifications when
the AD7329 is configured with the minimum VDD and VSS
supplies for a chosen analog input range, the throughput rate
should be decreased from the maximum throughput range (see
the Typical Performance Characteristics section).
The analog inputs can be configured as either eight single-ended
inputs, four true differential input pairs, four pseudo differential
inputs, or seven pseudo differential inputs. Selection can be made
by programming the mode bits, Mode 0 and Mode 1, in the
control register.
The serial clock input accesses data from the part and provides
the clock source for the successive approximation ADC. The
AD7329 has an on-chip 2.5 V reference. However, the AD7329
can also work with an external reference. On power-up, the
external reference operation is the default option. If the internal
reference is the preferred option, the user must write to the
reference bit in the control register to select the internal
reference operation.
The AD7329 also features power-down options to allow power
savings between conversions. The power-down modes are
selected by programming the on-chip control register as
described in the Modes of Operation section.
CONVERTER OPERATION
The AD7329 is a successive approximation analog-to-digital
converter built around two capacitive DACs. Figure 24 and
Figure 25 show simplified schematics of the ADC in single-
ended mode during the acquisition and conversion phases,
respectively. Figure 26 and Figure 27 show simplified schematics
of the ADC in differential mode during acquisition and
conversion phases, respectively. In both examples, the
MUXOUT+ pin is connected to the ADCIN+ pin, and the
MUXOUT− pin is connected to the ADCIN− pin. The ADC is
composed of control logic, a SAR, and capacitive DACs. In
Figure 24 (the acquisition phase), SW2 is closed and SW1 is in
Position A, the comparator is held in a balanced condition, and
the sampling capacitor array acquires the signal on the input.
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
AGND
SW2
SW1
A
B
CS
VIN0
Figure 24. ADC Acquisition Phase (Single Ended)
When the ADC starts a conversion (Figure 25), SW2 opens and
SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the capacitive DAC to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
AGND
SW2
SW1
A
B
CS
VIN0
Figure 25. ADC Conversion Phase (Single Ended)


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