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AD7328 Datasheet(PDF) 31 Page - Analog Devices

Part No. AD7328
Description  8-Channel, Software-Selectable True Bipolar Input, 12-Bit Plus Sign ADC
Download  36 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7328 Datasheet(HTML) 31 Page - Analog Devices

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AD7328
Rev. A | Page 31 of 36
SERIAL INTERFACE
Conversion data is clocked out of the AD7328 on each SCLK
falling edge. Data on the DOUT line consists of three channel
identifier bits, a sign bit, and a 12-bit conversion result. The
channel identifier bits are used to indicate which channel
corresponds to the conversion result.
Figure 53 shows the timing diagram for the serial interface of
the AD7328. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7328 during a conversion.
CS
The
signal initiates the data transfer and the conversion
process. The falling edge of CS
Three-State
If the Weak/
bit is set in the control register, rather
than returning to true three-state upon the 16
puts the track-and-hold into
hold mode and takes the bus out of three-state. The analog
input signal is then sampled. Once the conversion is initiated,
it requires 16 SCLK cycles to complete.
th SCLK falling
edge, the DOUT line is pulled weakly to the logic level corres-
ponding to ADD3 of the next serial transfer. This is done to
ensure that the MSB of the next serial transfer is set up in time
for the first SCLK falling edge after the
The track-and-hold goes back into track mode on the 14th SCLK
rising edge. On the 16
CS falling edge. If the
Weak/
th SCLK falling edge, the DOUT line returns
to three-state. If the rising edge of
Three-State bit is set to 0 and the DOUT line returns to
true three-state between conversions, then depending on the
particular processor interfacing to the AD7328, the ADD3 bit
may be valid in time for the processor to clock it in successfully.
If the Weak/
CS occurs before 16 SCLK cycles
have elapsed, the conversion is terminated and the DOUT line
returns to three-state. Depending on where the CS signal is brought
high, the addressed register may be updated.
Three-State bit is set to 1, then although the DOUT
line has been driven to ADD3 since the previous conversion, it
is nevertheless so weakly driven that another device could take
control of the bus. This will not lead to a bus contention issue
because, for example, a 10 kΩ pull-up or pull-down resistor is
sufficient to overdrive the logic level of ADD3. When the Weak/
Data is clocked into the AD7328 on the SCLK falling edge. The
three MSBs on the DIN line are decoded to select which register
is addressed. The control register is a 12-bit register. If the control
register is addressed by the three MSBs, the data on the DIN line
is loaded into the control on the 15th SCLK rising edge. If the se-
quence register or either of the range registers is addressed, the
data on the DIN line is loaded into the addressed register on the
11
Three-State bit is set to 1, the ADD3 is typically valid 9 ns after
the CS falling edge, compared with 14 ns when the DOUT line
returns to three-state at the end of the conversion.
th SCLK falling edge.
ADD1
1
234
5
13
14
15
16
WRITE
REG
SEL1
REG
SEL2
LSB
DON’T
CARE
MSB
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
t2
t6
t4
t9
t10
t3
t7
t5
t8
t1
tQUIET
tCONVERT
SCLK
CS
DOUT
THREE-
STATE
THREE-STATE
DIN
ADD2
3 IDENTIFICATION BITS
Figure 53. Serial Interface Timing Diagram (Control Register Write)


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