Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

AD7328 Datasheet(PDF) 6 Page - Analog Devices

Part No. AD7328
Description  8-Channel, Software-Selectable True Bipolar Input, 12-Bit Plus Sign ADC
Download  36 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

AD7328 Datasheet(HTML) 6 Page - Analog Devices

Zoom Inzoom in Zoom Outzoom out
 6 / 36 page
background image
AD7328
Rev. A | Page 6 of 36
TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external,
TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted.1
Table 3.
Limit at TMIN, TMAX
Description
Parameter
VCC < 4.75 V
VCC = 4.75 V to 5.25 V
Unit
VDRIVE ≤ VCC
fSCLK
50
50
kHz min
14
20
MHz max
tCONVERT
16 × tSCLK
16 × tSCLK
ns max
tSCLK = 1/fSCLK
tQUIET
75
60
ns min
Minimum time between end of serial read and next falling edge of CS
t1
12
5
ns min
Minimum CS pulse width
t22
25
20
ns min
CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
45
35
ns min
Unipolar input range (0 V to 10 V)
t3
26
14
ns max
Delay from CS until DOUT three-state disabled
t4
57
43
ns max
Data access time after SCLK falling edge
t5
0.4 × tSCLK
0.4 × tSCLK
ns min
SCLK low pulse width
t6
0.4 × tSCLK
0.4 × tSCLK
ns min
SCLK high pulse width
t7
13
8
ns min
SCLK to data valid hold time
t8
40
22
ns max
SCLK falling edge to DOUT high impedance
10
9
ns min
SCLK falling edge to DOUT high impedance
t9
4
4
ns min
DIN set-up time prior to SCLK falling edge
t10
2
2
ns min
DIN hold time after SCLK falling edge
tPOWER-UP
750
750
ns max
Power up from autostandby
500
500
μs max
Power up from full shutdown/autoshutdown mode, internal reference
25
25
μs typ
Power up from full shutdown/autoshutdown mode, external reference
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
) and timed from a voltage level of 1.6 V.
DRIVE
2 When using the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t at 20 ns, the mark space ratio needs to be limited to 50:50.
2
ADD1
1
2
3
4
5
13
14
15
16
WRITE
REG
SEL1
REG
SEL2
LSB
DON’T
CARE
MSB
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
t2
t6
t4
t9
t10
t3
t7
t5
t8
t1
tQUIET
tCONVERT
SCLK
CS
DOUT
THREE-
STATE
THREE-STATE
DIN
ADD2
3 IDENTIFICATION BITS
Figure 2. Serial Interface Timing Diagram


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn