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AD7327 Datasheet(PDF) 30 Page - Analog Devices

Part No. AD7327
Description  500 kSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
Download  36 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7327 Datasheet(HTML) 30 Page - Analog Devices

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AD7327
Rev. 0 | Page 30 of 36
AUTOSHUTDOWN MODE
(PM1 = 1, PM0 = 0)
Once the autoshutdown mode is selected, the AD7327 auto-
matically enters shutdown on the 15th SCLK rising edge. In
autoshutdown mode, all internal circuitry is powered down.
The AD7327 retains information in the registers during
autoshutdown. The track-and-hold is in hold mode during
autoshutdown. On the rising CS edge, the track-and-hold, which
was in hold during autoshutdown, returns to track as the AD7327
begins to power up. The power-up from autoshutdown is 500 μs.
When the control register is programmed to transition to
autoshutdown mode, it does so on the 15th SCLK rising edge.
Figure 50 shows the part entering autoshutdown mode. The
AD7327 automatically begins to power up on the CS rising
edge. The tPOWER-UP is required before a valid conversion, initiated
by bringing the CS signal low, can take place. Once this valid
conversion is complete, the AD7327 powers down again on the
15th SCLK rising edge. The CS signal must remain low again to
keep the part in autoshutdown mode.
AUTOSTANDBY MODE
(PM1 = 0, PM0 =1)
In autostandby mode, portions of the AD7327 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to auto-
shutdown but allows the AD7327 to power up much faster,
which allows faster throughput rates.
As is the case with autoshutdown mode, the AD7327 enters
standby on the 15th SCLK rising edge once the control register is
updated (see Figure 50). The part retains information in the
registers during standby. The AD7327 remains in standby until
it receives a CS rising edge. The ADC begins to power up on the
CS rising edge. On the CS rising edge, the track-and-hold,
which was in hold mode while the part was in standby, returns
to track.
The power-up time from standby is 700 ns. The user should
ensure that 700 ns have elapsed before bringing CS low to
attempt a valid conversion. Once this valid conversion is
complete, the AD7327 again returns to standby on the 15th
SCLK rising edge. The CS signal must remain low to keep the
part in standby mode.
Figure 50 shows the part entering autoshutdown mode. The
sequence of events is the same when entering autostandby
mode. In Figure 50, the power management bits are configured
for autoshutdown. For autostandby mode, the power
management bits, PM1 and PM0, should be set to 0 and 1,
respectively.
CS
116
15
1
16
15
SCLK
SDATA
DIN
VALID DATA
VALID DATA
DATA INTO CONTROL REGISTER
DATA INTO CONTROL REGISTER
tPOWER-UP
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
PM1 = 1, PM0 = 0
PART ENTERS SHUTDOWN MODE
ON THE 15TH RISING SCLK EDGE
AS PM1 = 1, PM0 = 0
PARTBEGINS TO POWER
UP ON CS RISING EDGE
THE PART IS FULLY POWERED UP
ONCE
tPOWER-UP HAS ELAPSED
Figure 50. Entering Autoshutdown/Autostandby Mode


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