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AD5934 Datasheet(PDF) 5 Page - Analog Devices

Part No. AD5934
Description  250 kSPS, 12-Bit Impedance Converter, Network Analyzer
Download  32 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5934 Datasheet(HTML) 5 Page - Analog Devices

 
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AD5934
Rev. 0 | Page 5 of 32
I2C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter2
Limit at TMIN, TMAX
Unit
Description
FSCL
400
kHz max
SCL clock frequency
t1
2. 5
μs min
SCL cycle time
t2
0. 6
μs min
tHIGH, SCL high time
t3
1. 3
μs min
tLOW, SCL low time
t4
0. 6
μs min
tHD, STA, start/repeated start condition hold time
t5
100
ns min
tSU, DAT, data setup time
t63
0. 9
μs max
tHD, DAT, data hold time
0
μs min
tHD, DAT, data hold time
t7
0. 6
μs min
tSU, STA, setup time for repeated start
t8
0. 6
μs min
tSU, STO, stop condition setup time
t9
1. 3
μs min
tBUF, bus free time between a stop and a start condition
t10
300
ns max
tF, rise time of SDA when transmitting
0
ns min
tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11
300
ns max
tF, fall time of SCL and SDA when transmitting
0
ns min
tF, fall time of SDA when receiving (CMOS compatible)
250
ns max
tF, fall time of SDA when receiving
20 + 0.1 CB4
ns min
tF, fall time of SCL and SDA when transmitting
CB
400
pF max
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization, not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) in order to bridge the undefined SCL’s falling edge.
4 CB is the total capacitance of one bus line in pF. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.
SCL
SDA
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t9
t3
t10
t11
t4
t4
t6
t2
t5
t7
t8
t1
Figure 2. I2C Interface Timing Diagram


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