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AD15252 Datasheet(PDF) 3 Page - Analog Devices

Part No. AD15252
Description  12-Bit, 65 MSPS, Dual ADC
Download  20 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD15252 Datasheet(HTML) 3 Page - Analog Devices

 
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AD15252
Rev. 0 | Page 3 of 20
ELECTRICAL CHARACTERISTICS
AVDD = 3.3 V, DRVDD = 2.5 V, encode = 65 MSPS, CLK_A = CLK_B, AIN = −9 dBFS differential input, TA= 25°C, unless otherwise
noted.
Table 1.
Parameter
Temp
Test Level
Min
Typ
Max
Unit
RESOLUTION
12
Bits
ACCURACY
No Missing Codes
25°C
IV
Guaranteed
Offset Error
25°C
I
−6
±1.7
+6
% FSR
Gain Error
25°C
I
−12.5
±2.0
+12.5
% FSR
Differential Nonlinearity (DNL)
Full
V
±0.35
LSB
Integral Nonlinearity (INL)
Full
V
±0.8
LSB
TEMPERATURE DRIFT
Offset Error
Full
V
±9
ppm/°C
Gain Error
Full
V
±172
ppm/°C
MATCHING CHARACTERISTICS
Offset Error
Full
V
±2.0
% FSR
Gain Error
Full
V
±1.0
% FSR
Input Referred Noise
Full
V
0.87
LSB rms
ANALOG INPUT
Input Range
Full
IV
296
mV p-p
Input Resistance (RIN)1
25°C
V
100
Ω
Input Capacitance (CIN)1
25°C
V
1.8
pF
CLOCK INPUTS
High Level Input Voltage (VIH)
Full
IV
2.0
V
Low Level Input Voltage (VIL)
Full
IV
0.8
V
High Level Input Current (IIH)
Full
IV
−10
+10
μA
Low Level Input Current (IIL)
Full
IV
−10
+10
μA
Input Capacitance (CIN)
Full
V
2
pF
LOGIC OUTPUTS
High Level Output Voltage (VOH)
Full
IV
2.49
V
Low Level Output Voltage (VOL)
Full
IV
0.2
V
INTERFACE TIMING
Maximum Conversion Rate
Full
VI
65
MSPS
Minimum Conversion Rate
Full
IV
1
MSPS
Clock Period (tC)
Full
V
15.4
ns
Clock Width High (tCH)
Full
IV
6.2
ns
Clock Width Low (tCL)
Full
IV
6.2
ns
Clock to Data (tOD)
Full
IV
2
6
ns
Pipeline Delay (Latency)
Full
V
7
Cycles
POWER SUPPLIES
Supply Voltages
AVDD
Full
IV
3.0
3.3
3.6
V
DRVDD
Full
IV
2.25
2.5
3.6
V
Supply Currents
AVDD
Full
VI
254
280
mA
DRVDD
Full
VI
12
15
mA
Total Power Dissipation
Full
VI
0.87
1.0
W


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