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AD15252 Datasheet(PDF) 1 Page - Analog Devices

Part No. AD15252
Description  12-Bit, 65 MSPS, Dual ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD15252 Datasheet(HTML) 1 Page - Analog Devices

 
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12-Bit, 65 MSPS, Dual ADC
AD15252
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
FEATURES
12-bit, 65 MSPS dual ADC
Differential input with 100 Ω input impedance
Full-scale analog input: 296 mV p-p
170 MHz, 3 dB bandwidth
SNR (−9 dBFS): 64 dBFS (70 MHz AIN), 64 dBFS (140 MHz AIN)
SFDR (−9 dBFS): 77 dBFS (70 MHz AIN), 73 dBFS (140 MHz AIN)
435 mW per channel
Dual parallel output buses
Out-of-range indicators
Independent clocks
Duty cycle stabilizer
Twos complement or offset binary data format
APPLICATIONS
Antijam GPS receivers
Wireless and wired broadband communications
Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
INA
LPF
DATA
BUS A
PDWNA
CLKA
INB
LPF
DATA
BUS B
PDWNB
DFS
CLKB
OEB_A
OEB_B
AD15252
OTR_A
OTR_B
Figure 1.
GENERAL DESCRIPTION
The AD15252 is a dual, 12-bit, 65 MSPS, analog-to-digital
converter (ADC). It features a differential front-end
amplification circuit followed by a sample-and-hold amplifier
and multistage pipeline ADC. It is designed to operate with a
3.3 V analog supply and a 2.5 V/3.3 V digital supply. Each input
is fully differential, ac-coupled, and terminated in 100 Ω input
impedances. The full-scale differential signal input range is
296 mV p-p.
Two parallel, 12-bit digital output buses provide data flow from
the ADCs. The digital output data is presented in either straight
binary or twos complement format. Out-of-range (OTR) signals
indicate an overflow condition, which can be used with the
most significant bit to determine low or high overflow. Dual
single-ended clock inputs control all internal conversion cycles.
A duty cycle stabilizer allows wide variations in the clock duty
cycle while maintaining excellent performance. The AD15252 is
optimized for applications in antijam global positioning
receivers and is well suited for communications applications.
PRODUCT HIGHLIGHTS
1.
Dual 12-bit, 65 MSPS ADC with integrated analog signal
conditioning optimized for antijam global positioning
system receiver (AJ-GPS) applications.
2.
Operates from a single 3.3 V power supply and features a
separate digital output driver supply to accommodate 2.5 V
and 3.3 V logic families.
3.
Packaged in a space-saving 8 mm × 8 mm chip scale
package ball grid array (CSP_BGA) and is specified over
the industrial temperature range (–40°C to +85°C).


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