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NCP5214A Datasheet(PDF) 23 Page - ON Semiconductor |
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NCP5214A Datasheet(HTML) 23 Page - ON Semiconductor |
23 / 31 page NCP5214A http://onsemi.com 23 Close loop system bandwidth can be calculated by: BW + R3 R1 VIN VRAMP 1 2 p L COUT (eq. 28) Since the ramp amplitude of the PWM modulator has a voltage feedforward function, the ramp amplitude is a function of VIN which can be determined by: VRAMP + 1.25 V ) 0.045 (VIN−5.0 V) (eq. 29) Below are some guidelines for setting the compensation components: 1. Set a value for R1 between 2.0 k W and 5.0 kW. 2. Set a target for the close loop bandwidth which should be less than 50% of the switching frequency. 3. Pick compensation DC gain (R3/R1) for desired close loop bandwidth. 4. Place 1st zero at half filter double pole. 5. Place 1st pole at ESR zero. 6. Place 2nd zero at filter double pole. 7. Place 2nd pole at half the switching frequency. By using the above equations and guidelines, the compensation components values can be determined by the equations below: R3 + 2 p BW VRAMP R1 L COUT VIN (eq. 30) C2 + 2 L COUT R3 (eq. 31) C1 + C2 R3 C2 ESR COUT * 1 (eq. 32) R4 + R1 p fSW L COUT * 1 (eq. 33) C3 + 1 p R4 fSW (eq. 34) The modulator and filter gain, compensation gain, and close loop gain asymptotic Bode plot can be drawn by the calculated results to check the compensation gain and close loop gain obtained. An example of asymptotic Bode plot is shown in Figure 40. The phase of the output filter can be calculated by: Phase(Filter) + − tan −1(2pf ESR COUT)− tan −1 2 pf ESR ) DCR COUT (2 pf)2 L COUT−1 (eq. 35) where the DCR of the inductor can be neglected if the DCR is small. The phase of the Type III compensation network can be calculated by: Phase(TypeIII) + −90° ) tan −1(2pf R3 C2)− tan −1 2pf R3 C1 C2 C1 ) C2 (eq. 36) ) tan −1(2pf (R1 ) R4) C3)− tan −1(2pf R4 C3) The close loop phase can be calculated by summing the filter phase and compensation phase: Phase(CloseLoop) + Phase(Filter) ) Phase(TypeIII) (eq. 37) Then the close loop phase margin can be estimated by: Phase(Margin) + Phase(CloseLoop) * (*180°) (eq. 38) It should be checked that closed loop gain has a 0 dB gain crossing with −20 dB/decade slope and a phase margin of 45 ° or greater. The compensation components values may require some adjustment to meet these requirements. Besides, the compensation gain should be checked with the error amplifier open loop gain to make sure that it is bounded by the error amplifier open loop gain. The poles and zeros locations and hence the compensation network components values may need to be further fine tuned after actual system testing and analysis. Feedback Resistor Divider The output voltage of the buck regulator can be adjusted by the feedback resistor divider formed by R1 and R2. Once the value of R1 is selected when determining the compensation components, the value of R2 can be obtained by: R2 + 0.8 R1 VOUT−0.8 (eq. 39) It is recommended to adjust the value of R2 to fine−tune the output voltage when it is necessary. The value of R1 should not be changed since the compensation DC gain and the 2nd zero break frequency of the compensation gain are contributed by R1. If the value of R1 is changed, the compensation, the close loop bandwidth and phase margin, and the system stability will be affected. Besides, it is recommended to use resistors with at least 1% tolerance for R1 and R2. Soft−Start of Buck Regulator A VDDQ soft−start feature is incorporated in the device to prevent surge current from power supply and output voltage overshoot during power up. When VDDQEN, VCCA, and VOCDDQ rise above their respective upper threshold voltages, the external soft−start capacitor CSS will be charged up by a constant current source, Iss. When the soft−start voltage (Vcss) rises above the SS_EN voltage ( X50 mV), the BGDDQ and TGDDQ will start switching and VDDQ output will ramp up with VFBDDQ following the soft−start voltage. When the soft−start voltage reaches the SS_OK voltage ( XVref + 50 mV), the soft−start of |
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