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NCP1580 Datasheet(PDF) 6 Page - ON Semiconductor

Part No. NCP1580
Description  Low Voltage Synchronous Buck Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP1580 Datasheet(HTML) 6 Page - ON Semiconductor

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The NCP1580 is an 8−pin PWM controller intended for
DC−DC conversion from 5.0 V and 12 V buses. The
NCP1580 has a 1.5 A internal floating gate driver circuit
synchronous−rectifier buck topology. The internal floating
gate driver simplifies design, improves performance, and
minimizes board area. The output voltage of the converter
can be precisely regulated down to 800 mV
$ 1.5% when
the VFB pin is tied to VOUT. The switching frequency, which
is internally set to 350 kHz, and soft−start are completely
integrated. The voltage error amplifier features a 10 MHz
unity gain bandwidth and 4 V/
msec slew rate for fast
transient response.
Duty Cycle and Maximum Pulse Width Limits
In steady state DC operation, the duty cycle will stabilize
at an operating point defined by the ratio of the input to the
output voltage. The NCP1580 can achieve a 90% duty cycle.
There is a built in off−time which ensures that the bootstrap
supply is charged every cycle. The NCP1580, which is
capable of a 100 nsec minimum pulse width (typ), can allow
a 12 V to 1.0 V conversion at 350 kHz.
Input Voltage Range (VCC and BST)
The input voltage range for both VCC and BST is 4.5 V to
13.2 V with respect to GND and PHASE, respectively.
Although BST is rated at 13.2 V with respect to PHASE, it
can also tolerate 26.5 V with respect to GND.
Normal Shutdown Behavior
Normal shutdown occurs when the IC stops switching
because the input supply reaches UVLO threshold. In this
case, switching stops, the internal SS is discharged, and all
GATE pins go low. The switch node enters a high impedance
state and the output capacitors discharge through the load
with no ringing on the output voltage.
Internal Soft−Start
The NCP1580 features an internal soft−start function,
which reduces inrush current and overshoot of the output
voltage. Figure 10 shows a typical soft−start sequence.
Soft−start is achieved by ramping up the internal soft−start
voltage (VSS) which is applied to the input of the error
amplifier. This ramp is generated by applying 0.5
mA to a
100 pf capacitor for 1
msec on every fourth clock pulse. This
sequence begins once VCC surpasses its UVLO threshold
(see Figure 11). The typical soft−start time is 2 msec. The
internal soft−start voltage is held low when the part is in
Figure 10. Normal Startup
4.2 V
2 ms
Normal Operation
Figure 11. Achieving Internal Soft−Start
4.2 V
5 mV

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