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AD5678 Datasheet(PDF) 22 Page - Analog Devices

Part No. AD5678
Description  4 × 12-Bit and 4 × 16-Bit Octal DAC with On-Chip Reference in 14-Lead TSSOP
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5678 Datasheet(HTML) 22 Page - Analog Devices

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AD5678
Rev. A | Page 22 of 28
INPUT SHIFT REGISTER
The input shift register is 32 bits wide. The first four bits are
don’t cares. The next four bits are the command bits, C3 to C0
(see Table 7), followed by the 4-bit DAC address bits, A3 to A0
(see Table 8), and finally the 16-/12-bit data-word. The data-
word comprises the 16-/12-bit input code followed by four or
eight don’t care bits for the AD5678 DAC A, B, G, H and
AD5678 DAC C, D, E, F, respectively (See Figure 47 and Figure
48). These data bits are transferred to the DAC register on the
32nd falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for
32 falling edges of SCLK, and the DAC is updated on the 32nd
falling edge and rising edge of SYNC. However, if SYNC is
brought high before the 32nd falling edge, this acts as an
interrupt to the write sequence. The shift register is reset, and
the write sequence is seen as invalid. Neither an update of the
DAC register contents nor a change in the operating mode
occurs—see Figure 49.
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
XX
X
DB31 (MSB)
DB0 (LSB)
DATA BITS
Figure 47. AD5678 Input Register Content for DAC A, B, G , H
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXX
XXXX
X
X
XX
X
DB31 (MSB)
DB0 (LSB)
DATA BITS
Figure 48. AD5678 Input Register Content for DAC C, D, E, F
SCLK
DIN
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
DB31
DB0
SYNC
Figure 49. SYNC Interrupt Facility


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