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AD5663 Datasheet(PDF) 5 Page - Analog Devices

Part No. AD5663
Description  2.7 V to 5.5 V, 250 uA, Rail-to-Rail Output, Dual 16-Bit nanoDAC
Download  24 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5663 Datasheet(HTML) 5 Page - Analog Devices

 
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AD5663
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.1
Table 4.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
t12
20
ns min
SCLK cycle time
t2
9
ns min
SCLK high time
t3
9
ns min
SCLK low time
t4
13
ns min
SYNC to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
15
ns min
Minimum SYNC high time
t9
13
ns min
SYNC rising edge to SCLK fall ignore
t10
0
ns min
SCLK falling edge to SYNC fall ignore
t11
10
ns min
LDAC pulse width low
t12
15
ns min
SCLK falling edge to LDAC rising edge
t13
5
ns min
CLR pulse width low
t14
0
ns min
SCLK falling edge to LDAC falling edge
t15
300
ns max
CLR pulse activation time
1 Guaranteed by design and characterization; not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
t4
t3
SCLK
SYNC
DIN
t1
t2
t5
t6
t7
t8
DB23
t9
t10
t11
t12
LDAC1
LDAC2
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
CLR
t13
t15
VOUT
DB0
Figure 2. Serial Write Operation


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