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AD5622YKSZ-2500RL7 Datasheet(PDF) 4 Page - Analog Devices |
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AD5622YKSZ-2500RL7 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 24 page  AD5602/AD5612/AD5622 Rev. B | Page 4 of 24 A, B, W, Y Versions1 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS VDD 2.7 5.5 V IDD (Normal Mode) DAC active and excluding load current VDD = 4.5 V to 5.5 V 75 100 μA VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 60 90 μA VIH = VDD and VIL = GND IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V 0.3 1 μA VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 0.15 1 μA VIH = VDD and VIL = GND POWER EFFICIENCY IOUT/IDD 96 % ILOAD = 2 mA, VDD = 5 V 1 Temperature ranges for A, B versions: −40°C to +125°C, typical at 25°C. 2 Linearity calculated using a reduced code range 64 to 4032. 3 Guaranteed by design and characterization, not production tested. I2C TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1 Table 3. Limit at TMIN, TMAX Parameter Conditions2 Min Max Unit Description fSCL3 Standard mode 100 KHz Serial clock frequency Fast mode 400 KHz High speed mode, CB = 100 pF 3.4 MHz High speed mode, CB = 400 pF 1.7 MHz t1 Standard mode 4 μs tHIGH, SCL high time Fast mode 0.6 μs High speed mode, CB = 100 pF 60 ns High speed mode, CB = 400 pF 120 ns t2 Standard mode 4.7 μs tLOW, SCL low time Fast mode 1.3 μs High speed mode, CB = 100 pF 160 ns High speed mode, CB = 400 pF 320 ns t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns High speed mode 10 ns t4 Standard mode 0 3.45 μs tHD;DAT, data hold time Fast mode 0 0.9 μs High speed mode, CB = 100 pF 0 70 ns High speed mode, CB = 400 pF 0 150 ns t5 Standard mode 4.7 μs tSU;STA, set-up time for a repeated start condition Fast mode 0.6 μs High speed mode 160 ns t6 Standard mode 4 μs tHD;STA, hold time (repeated) start condition Fast mode 0.6 μs High speed mode 160 ns t7 Standard mode 4.7 μs tBUF, bus free time between a stop and a start condition Fast mode 1.3 μs |
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Similar Description - AD5622YKSZ-2500RL7 |
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