ADUM3100 datasheet(3/16 Pages) AD

Part #	ADUM3100

Description	Digital Isolator, Enhanced System-Level ESD Reliability

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ADuM3100

Rev. A | Page 3 of 16

ELECTRICAL SPECIFICATIONS, 5 V OPERATION1

4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,

unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

DC SPECIFICATIONS

Input Supply Current, Quiescent

IDD1 (Q)

1.3

1.8

mA

VI = 0 V or VDD1

Output Supply Current, Quiescent

IDD2 (Q)

0.15

0.25

mA

VI = 0 V or VDD1

Input Supply Current (25 Mbps)

(See Figure 4)

IDD1 (25)

3.2

4.5

mA

12.5 MHz logic signal freq.

Output Supply Current2 (25 Mbps)

(See Figure 5)

IDD2 (25)

0.6

1.1

mA

12.5 MHz logic signal freq.

Input Supply Current (100 Mbps)

(See Figure 4)

IDD1 (100)

10

15

mA

50 MHz logic signal freq.

Output Supply Current2 (100 Mbps)

(See Figure 5)

IDD2 (100)

2.1

2.9

mA

50 MHz logic signal freq.,

ADuM3100BR only

Input Current

II

−10

+0.01

+10

μA

0 ≤ VIN ≤ VDD1

Logic High Output Voltage

VOH

VDD2 − 0.1

5.0

V

IO = −20 μA, VI = VIH

VDD2 − 0.8

4.6

V

IO = –4 mA, VI = VIH

Logic Low Output Voltage

VOL

0.0

0.1

V

IO = 20 μA, VI = VIL

0.03

0.1

V

IO = 400 μA, VI = VIL

0.3

0.8

V

IO = 4 mA, VI = VIL

SWITCHING SPECIFICATIONS

For ADuM3100AR

Minimum Pulse Width3

PW

40

ns

CL = 15 pF, CMOS signal

levels

Maximum Data Rate4

25

Mbps

CL = 15 pF, CMOS signal

levels

For ADuM3100BR

Minimum Pulse Width4

PW

6.7

10

ns

CL = 15 pF, CMOS signal

levels

Maximum Data Rate4

100

150

Mbps

CL = 15 pF, CMOS signal

levels

For All Grades

Propagation Delay Time to Logic Low

Output5, 6 (See Figure 6)

tPHL

10.5

18

ns

CL = 15 pF, CMOS signal

levels

Propagation Delay Time to Logic High

Output5, 6 (See Figure 6)

tPLH

10.5

18

ns

CL = 15 pF, CMOS signal

levels

Pulse-Width Distortion |tPLH − tPHL|6

PWD

0.5

2

ns

CL = 15 pF, CMOS signal

levels

Change vs. Temperature7

3

ps/°C

CL = 15 pF, CMOS signal

levels

Propagation Delay Skew (Equal Temperature)6, 8

tPSK1

8

ns

CL = 15 pF, CMOS signal

levels

Propagation Delay Skew (Equal Temperature,

Supplies)6, 8

tPSK2

6

ns

CL = 15 pF, CMOS signal

levels

Output Rise/Fall Time

tR, tF

3

ns

CL = 15 pF, CMOS signal

levels

Common-Mode Transient Immunity at

Logic Low/High Output9

|CML|,

|CMH|

25

35

kV/μs

VI = 0 or VDD1, VCM = 1000 V

Input Dynamic Supply Current10

IDDI (D)

0.09

mA/Mbps

Output Dynamic Supply Current10

IDDO (D)

0.02

mA/Mbps

See notes on Page 6

.

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