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ADUM3100 Datasheet(PDF) 6 Page - Analog Devices

Part No. ADUM3100
Description  Digital Isolator, Enhanced System-Level ESD Reliability
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADUM3100 Datasheet(HTML) 6 Page - Analog Devices

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ADuM3100
Rev. A | Page 6 of 16
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Change vs. Temperature7
5 V/3 V Operation
3
ps/ºC
CL = 15 pF, CMOS signal levels
3 V/5 V Operation
10
ps/ºC
CL = 15 pF, CMOS signal levels
Propagation Delay Skew (Equal Temperature)6, 8
tPSK1
5 V/3 V Operation
12
ns
CL = 15 pF, CMOS signal levels
3 V/5 V Operation
15
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew (Equal Temperature,
Supplies)6, 8
tPSK2
5 V/3 V Operation
9
ns
CL = 15 pF, CMOS signal levels
3 V/5 V Operation
12
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR, tf
3
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic Low/High Output9
|CML|, |CMH|
25
35
kV/μs
VI = 0 or VDD1, VCM = 1000 V,
transient magnitude = 800 V
Input Dynamic Supply Current per Channel10
IDDI (D)
5 V/3 V Operation
0.09
mA/Mbps
3 V/5 V Operation
0.08
mA/Mbps
Output Dynamic Supply Current per Channel10
IDDO (D)
5 V/3 V Operation
0.01
mA/Mbps
3 V/5 V Operation
0.02
mA/Mbps
1 All voltages are relative to their respective ground.
2 Output supply current values are with no output load present. See Figure 4 and Figure 5 for information on supply current variation with logic signal frequency. See
the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the
rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
6 Because the input thresholds of the ADuM3100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse-width
distortion can be affected by slow input rise/fall times. See the System-Level ESD Considerations and Enhancements section and Figure 13 to Figure 17 for information
on the impact of given input rise/fall times on these parameters.
7 Pulse-width distortion change vs. temperature is the absolute value of the change in pulse-width distortion for a 1°C change in operating temperature.
8 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the
recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
9 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range
over which the common-mode is slewed.
10 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 4 and Figure 5 for information on
supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.


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