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NCP1381 Datasheet(PDF) 6 Page - ON Semiconductor

Part No. NCP1381
Description  Low−Standby High Performance PWM Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP1381 Datasheet(HTML) 6 Page - ON Semiconductor

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The NCP1381 includes all necessary features to help
building a rugged and safe switching power supply featuring
an extremely low standby power. The below bullets detail
the benefits brought by implementing the NCP1381
Current−modeoperation with Quasi−Resonant
Operation: Implementing peak current mode control,
the NCP1381 waits until the drain−source voltage
crosses a minimum level. This is the quasi−resonance
approach, minimizing both EMI radiations and
capacitive losses.
Over Power Protection: Using a voltage image of the
bulk level, via the brown−out divider, the designer can
select a resistor which, placed in series with the current
sense information, provides an efficient line
compensation method.
Frequency Clamp: The controller monitors the sum of
ton and toff, providing a real frequency clamp. Also the
ton maximum duration is safely limited to 50
ms in case
the peak current information is lost. If the maximum
ton limit is reached, then the controller stops all pulses
and enters a safe auto−recovery burst mode.
Blanking Time: To prevent false tripping with energetic
leakage spikes, the controllers includes a 3
ms blanking
time after the toff event.
Go−to−Standby Signal for PFC Front Stage: The
NCP1381 includes an internal low impedance switch
connected between Pin 10 (VCC) and Pin 11 (GTS).
The signal delivered by Pin 11 being of low impedance,
it becomes possible to connect PFC’s VCC directly to
this pin and thus avoid any complicated interface
circuitry between the PWM controller and the PFC
front−end section. In normal operation, Pin 11 routes
the PWM auxiliary VCC to the PFC circuit which is
directly supplied by the auxiliary winding. When the
SMPS enters skip−cycle at low output power levels, the
controller detects and confirms the presence of the skip
activity by monitoring the signal applied on its pin
ADJ_GTS (typically FB signal) and opens Pin 11,
shutting down the front−end PFC stage. When this
signal level increases, e.g. when the SMPS goes back to
a normal output power, Pin 11 immediately (without
delay) goes back to a low impedance state. Finally, in
short−circuit conditions, the PFC is disabled to lower
the stress applied to the PWM main switch.
Low Startup−Current: Reaching a low no−load standby
power represents a difficult exercise when the
controller requires an external, lossy, resistor connected
to the bulk capacitor. Due to a novel silicon
architecture, the startup current is guaranteed to be less
than 15
mA maximum, helping the designer to reach a
low standby power level.
Skip−cycle Capability: A continuous flow of pulses in
not compatible with no−load standby power
requirements. Slicing the switching pattern in bunch of
pulses drastically reduces overall losses but can, in
certain cases, bring acoustic noise in the transformer.
Due to a skip operation taking place at low peak currents
only, no mechanical noise appears in the transformer.
This is further strengthened by ON Semiconductor’s
Soft−Skip technique, which forces the peak current in
skip to gradually increase. In case the default skip value
would be too large, connecting a resistor to the Pin 6 will
reduce or increase the skip cycle level. Adjusting the
skip level also adjusts the maximum switching frequency
before skip occurs.
Soft−Start: A circuitry provides a soft−start sequence
which precludes the main power switch from being
stressed upon startup. This soft−start is internal and
reaches 5 ms typical.
Overvoltage Protection: By sensing the plateau level
after the power switch has opened, the controller can
detect an overvoltage condition through the auxiliary
reflection of the output voltage. If an OVP is sensed,
the controller stops all pulses and permanently stays
latched until the VCC is cycled down below 4.0 V.
External Latch Input: By permanently monitoring
Pin 5, the controller detects when its level rises above
3.5 V, e.g. in presence of a fault condition like an OTP.
This fault is permanently latched−off and needs the
VCC to go down below 4.0 V to reset, for instance when
the user unplugs the SMPS.
Brown−out Detection: By monitoring the level on Pin 2
during normal operation, the controller protects the
SMPS against low mains condition. When the Pin 2
level falls below 240 mV, the controllers stops pulsing
until this level goes back to 500 mV to prevent any
instability. During brown−out conditions, the PFC is not
Short−circuit Protection: Short−circuit and especially
overload protection are difficult to implement when a
strong leakage inductance between auxiliary and power
windings affects the transformer (the auxiliary winding
level does not properly collapse in presence of an
output short). Here, every time the internal 0.8 V
maximum peak current limit is activated, an error flag
is asserted and a time period starts, due to an external
timing capacitor. If the voltage on the capacitor reaches
4.0 V (after 90 ms for a 220 nF capacitor) while the
error flag is still present, the controller stops the pulses
and goes into a latch−off phase, operating in a
low−frequency burst−mode. As soon as the fault
disappears, the SMPS resumes its operation. The
latchoff phase can also be initiated, more classically,
when VCC drops below VCCOFF (10 V typical).

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