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NCP1282 Datasheet(PDF) 3 Page - ON Semiconductor

Part No. NCP1282
Description  High Performance Active Clamp/Reset PWM Controller Featuring 500 V Startup
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com

NCP1282 Datasheet(HTML) 3 Page - ON Semiconductor

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Connect the input line voltage directly to this pin to enable the internal startup regulator. A constant cur-
rent source supplies current from this pin to the capacitor connected to the VAUX pin, eliminating the need
for a startup resistor. The charge current is typically 10 mA. Maximum input voltage is 500 V.
Input supply voltage is scaled down and sampled by means of a resistor divider. The same pin is used
for both undervoltage (UV) and overvoltage (OV) detection using a novel architecture (patent pending).
The minimum and maximum input supply voltage thresholds are adjusted independently. A UV condition
exists if the UVOV voltage is below 2.0 V and an OV condition exists if the UVOV voltage exceeds 3.0 V.
The undervoltage threshold is trimmed during manufacturing to obtain "3% accuracy allowing a tighter
power stage design. Both the UV and OV detectors have a 100 mV hysteresis.
An external R−C divider from the input line generates the Feedforward Ramp. This ramp is used by the
PWM comparator to set the duty cycle, thus providing direct line regulation. An internal pulldown transis-
tor discharges the external capacitor every cycle. Once discharged, the capacitor is effectively grounded
until the next cycle begins.
Overcurrent sense input. If the CS voltage exceeds 0.5 V the converter operates in cycle−by−cycle cur-
rent limit. Once a current limit pulse is detected, the cycle skip timer is enabled. Internal leading edge
blanking pulse prevents nuisance triggering during normal operation. The leading edge blanking is dis-
abled during soft−start and output overload conditions to improve the response to faults.
Control circuit ground. All control and timing components that connect to GND should have the shortest
loop possible to this pin to improve noise immunity.
An external RT−CT divider from VREF sets the operating frequency and maximum duty cycle of OUT1.
The maximum operating frequency is 1.0 MHz. A sawtooth Ramp between 2.0 V and 3.0 V is generated
by sequentially charging and discharging CT. The peak and valley of the Ramp are accurately controlled
to provide precise control of the duty cycle and frequency. The outputs are disabled during the CT dis-
charge time.
Proprietary bidirectional frequency synchronization architecture allows two NCP1282 devices to syn-
chronize together. The lower frequency device becomes the slave. It can also synchronize to an external
Precision 5.0 V reference. Maximum output current is 5.0 mA. It is required to bypass the reference with
a capacitor. The recommended capacitance range is between 0.047 mF and 1.0 mF.
The error signal from an external error amplifier is fed to this input and compared to the Feedforward
Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM Compara-
tor inverting input. An internal pullup resistor allows direct connection to an optocoupler.
A 20 mA current source charges the external capacitor connected to this pin. Duty cycle is limited during
startup by comparing the voltage on this pin to the Feedforward Ramp. Under steady state conditions,
the SS voltage is approximately 3.8 V. Once a UV, OV, low VAUX, overtemperature or cycle skip fault is
detected, the SS capacitor is discharged in a controlled manner with a 100 mA current source. The duty
cycle is then slowly reduced until reaching 0%.
An external resistor between this pin and GND sets the overlap time delay between OUT1 and OUT2
The converter is disabled if a continuous overcurrent condition exists. The time to determine the fault and
the time the converter is disabled are programmed by the capacitor (CCSKIP) connected to this pin. The
cycle skip timer is enabled after a current limit fault is detected. Once enabled, CCSKIP is charged with a
100 mA source. If the overcurrent fault is removed before entering the soft−stop mode, the capacitor is
discharged with a 10 mA source. Once CCSKIP reaches 3.0 V, the converter enters a soft−stop mode and
CCSKIP is discharged with a 10 mA source. The converter is re−enabled once CCSKIP reaches 0.5 V. If
the condition resulting in overcurrent is cleared during this phase, CCSKIP discharges to 0 V. Otherwise, it
starts charging from 0.5 V, setting up a hiccup mode operation.
Secondary output of the PWM Controller. It can be used to drive an active clamp/reset switch, a synchro-
nous rectifier topology, or both. OUT2 has an adjustable leading and trailing edge overlap delay against
OUT1. OUT2 has source and sink resistances of 12 W (typ.). OUT2 is designed to handle up to 1.0 A.
Ground connection for OUT1 and OUT2. Tie to the power stage return with a short loop.
Main output of the PWM Controller. OUT1 has a source resistance of 4.0 W (typ.) and a sink resistance
of 2.5 W (typ.). OUT1 is designed to handle up to 2.5 A. OUT1 trails OUT2 during a low to high transition
and leads OUT2 during a high to low transition.
Positive input supply. This pin connects to an external capacitor for energy storage. An internal current
source supplies current from Vin to this pin. Once the voltage on VAUX reaches approximately 11.0 V, the
current source turns OFF and the outputs are enabled. Once VAUX reaches 9.5 V the startup circuit is
enabled and the controller enters the soft−stop mode. The outputs are immediately disabled if VAUX
reaches 8.5 V. During normal operation, power is supplied to the IC via this pin by means of an auxiliary
winding. The startup circuit is disabled once the voltage on the VAUX pin exceeds 11.0 V. If the VAUX
voltage drops below 1.2 V (typ), the startup current is reduced to 200 mA.

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