Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

NCP1239 Datasheet(PDF) 24 Page - ON Semiconductor

Part No. NCP1239
Description  Low−Standby High Performance PWM Controller
Download  38 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo 

NCP1239 Datasheet(HTML) 24 Page - ON Semiconductor

Zoom Inzoom in Zoom Outzoom out
 24 / 38 page
background image
NCP1239
http://onsemi.com
24
If by design we have selected a 47
mF VCC capacitor, it
becomes easy to evaluate the burst period and its duty−cycle.
This can be done by properly identifying all time events on
Figure 42 and applying the classical formula: t = C *
DV / i.
To simplify, let’s consider t1 starts while VCC = VCCOFF.
Then:
t1: I = ICC3 = 400 mA, DV= 11.2 – 6.9 = 3 V !
t1 = 505 ms
t2: I = 3.6 mA, DV= 16.4 – 6.9 = 9.5 V ! t2 = 124 ms
t3: I = 400 mA, DV= 16.4 – 11.2 = 5.2 V ! t3 = 611 ms
t’1 = t1= 505 ms
t’2 = t2 = 124 ms
The total period duration is thus the sum of all these events
which leads to Tfault = 1793 ms. If Tpulse = 100 ms, then
our burst duty−cycle equals 100/(1869 + 100)
≈ 5%, which
is excellent.
In fact, the calculation assumption, t1 starts while
VCC = VCCOFF, gives the worse case since the duty cycle is
calculated in the case where Tpulse exactly equals the active
phase duration (switching period when VCC decreases from
VCCON to VCCOFF).
In fact, Tpulse is generally:
− shorter than the switching phase period. In this
case, t1 is longer since the latched off phase starts
earlier (at a VCC higher than VCCOFF). As a
consequence, the final duty cycle is lower than
previously estimated,
− longer than the switching phase period. In this case,
the circuit detects an overload condition simply
because VCC drops below VCCOFF (11.2 V) before
the fault timer has elapsed. Tpulse is lower than 100
ms and as a result the duty cycle is also lower.
(Major) Fault Detection and Latched Off Mode
The
NCP1239
features
a
fast
comparator
that
permanently monitors the “Fault Detect” pin level. If for any
reason this level exceeds 2.4 V (typical), the part
immediately stops oscillating and stays latched off until the
user cycles down the power supply. This enables the SMPS
designer to externally shut down the part in particular when
a major default occurs, e.g. an Overvoltage Protection
(OVP). Figure 43 shows what happens when the part is
latched:
VCCOFF
Figure 43.
Drv
Latch−off phase level
Logic reset level
Pin 3
Stop!
2.4 V
When Vpin3 exceeds 2.4 V, NCP1239 permanently latches−off the output pulses
0until its VCC goes below 4 V. The figure can
illustrate a case where a thermistor supplied by REF5V is connected to Pin 3 to detect excessive temperatures of the application
(refer to application schematic).
The user has unplugged, reset!
VCC
VCCON


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn