AD5522 datasheet(12/45 Pages) AD

Part #	AD5522

Description	Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs

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AD5522

Preliminary Technical Data

Rev. PrL | Page 12 of 45

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

MEASVH1

CFF3

CCOMP3

AGND

GUARD1

AVDD

GUARDIN1

/DUTGND1

FOH1

EXTMEASIH1

GUARDIN3

/DUTGND3

EXTMEASIH3

EXTMEASIL3

FOH3

AVDD

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

CFF1

EXTMEASIL1

MEASVH3

CCOMP1

GUARD3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

EXTMEASIH2

GUARD0

EXTMEASIL2

FOH2

GUARD2

GUARDIN2

/DUTGND2

MEASVH2

AGND

FOH0

EXTMEASIL0

MEASVH0

EXTMEASIH0

AVDD

GUARDIN0

/DUTGND0

AVDD

CFF2

CCOMP2

CFF0

CCOMP0

AD5522

TOP VIEW

EXPOSED PADONBOTTOM

(Not to Scale)

Figure 8. Pin Configuration (Exposed Pad on bottom of package)

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

Bottom

Top

Exposed Pad

The exposed pad is electrically connected to AVSS.

TQFP with exposed pad on BOTTOM: For enhanced thermal, electrical and board level

performance, the exposed paddle on the bottom of the package should be soldered to a

corresponding thermal land paddle on the PCB.

22, 39, 62,

67, 79,

2, 14, 19,

42,59,

AVSS(0-4)

Negative analog supply voltage

1, 20, 41, 60,

74

7, 21, 40,

61, 80

AVDD(0-4)

Positive analog supply voltage

33

48

LOAD

Active low logic input used for synchronizing updates within one device or across a group

of devices. If synchronization is not required, LOAD may be tied low and updates to DAC

channels or PMU modes will happen as they are presented to the device. See the BUSY and

LOAD FUNCTIONS section for detailed information.

34

47

DVCC

Digital supply voltage

10, 11, 50,

51, 69

12, 30, 31,

70, 71

AGND

Analog ground, reference points for force and measure circuitry

30

51

DGND

Digital ground reference point.

23

58

BUSY

Open Drain active low input/output indicating the status of interface.

24

57

SCLK

Clock input, active falling edge

25

56

CPOL0/ SCLK

Comparator output low in SPI mode and SCLK in LVDS interface mode

26

55

CPOH0/ SDI

Comparator output high in SPI mode and SDI in LVDS interface mode

27

54

SDI

Serial data input

28

53

SYNC

Frame sync, active low

29

52

CPOL1/ SYNC

Comparator output low in SPI mode and SYNC in LVDS interface mode

31

50

CPOH1/SDO

Comparator output high in SPI mode and SDO in LVDS interface mode

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