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AD5522 Datasheet(PDF) 6 Page - Analog Devices

Part No. AD5522
Description  Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD5522 Datasheet(HTML) 6 Page - Analog Devices

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AD5522
Preliminary Technical Data
Rev. PrL | Page 6 of 45
Parameter
Min
Typ1
Max
Units
Test Conditions/Comments
FORCE AMPLIFIER
Slew Rate2
0.4
V/us
Ccomp=100pF, Cff=220pF, Cload=200pF
Gain Bandwidth2
1
MHz
Ccomp=100pF, Cff=220pF, Cload=200pF
Max stable load Capacitance2
10,000
pF
CCOMP = 100pF. Larger Load cap requires larger CCOMP
FV SETTLING TIME TO 0.05% OF FSVR
FS step
64mA Range2
TBD
40
µs
Ccomp=100pF, Cff=220pF, Cload=200pF
2mA range2
TBD
40
µs
Ccomp=100pF, Cff=220pF, Cload=200pF
200µA range2
TBD
40
µs
Ccomp=100pF, Cff=220pF, Cload=200pF
20µA range2
TBD
80
µs
Ccomp=100pF, Cff=220pF, Cload=200pF
5µA range2
TBD
300
µs
Ccomp=100pF, Cff=220pF, Cload=200pF
MI SETTLING TIME TO 0.05% OF FSCR
FS step
64mA Range2
TBD
TBD
µs
Ccomp=100pF, Cff=220pF, Cload=200pF
2mA range2
TBD
TBD
µs
Ccomp=100pF, Cff=220pF, Cload=200pF
200µA range2
TBD
TBD
µs
Ccomp=100pF, Cff=220pF, Cload=200pF
20µA range2
TBD
TBD
µs
Ccomp=100pF, Cff=220pF, Cload=200pF
5µA range2
TBD
TBD
µs
Ccomp=100pF, Cff=220pF, Cload=200pF
FI SETTLING TIME TO 0.05% OF FSCR
FS step
64mA Range2
30
TBD
µs
Ccomp=100pF, Cload=200pF
2mA range2
30
TBD
µs
Ccomp=100pF, Cload=200pF
200µA range2
80
TBD
µs
Ccomp=100pF, Cload=200pF
20µA range2
680
TBD
µs
Ccomp=100pF, Cload=200pF
5µA range2
3000
TBD
µs
Ccomp=100pF, Cload=200pF
MV SETTLING TIME TO .05% OF FSVR
FS step
64mA Range2
TBD
TBD
µs
Ccomp=100pF, Cload=200pF
2mA range2
TBD
TBD
µs
Ccomp=100pF, Cload=200pF
200µA range2
TBD
TBD
µs
Ccomp=100pF, Cload=200pF
20µA range2
TBD
TBD
µs
Ccomp=100pF, Cload=200pF
5µA range2
TBD
TBD
µs
Ccomp=100pF, Cload=200pF
DAC SPECIFICATIONS
Resolution
16
Bits
Voltage Output Span2
22.5
V
VREF=5V, within a range of -16.25 to 22.5V
Differential Nonlinearity2
-1
1
LSB
Guaranteed monotonic by design over temperature.
COMPARATOR DAC DYNAMIC
SPECIFICATIONS
Output Voltage Settling Time2
1.5
µs
1V change to ±1 LSB.
Slew Rate2
5
V/µs
Digital-to-Analog Glitch Energy2
20
nV-s
Glitch Impulse Peak Amplitude2
15
mV
REFERENCE INPUT
VREF DC Input Impedance
1
MΩ
Typically 100 MΩ.
VREF Input Current
-10
10
µA
Per input. Typically ±30 nA.
VREF Range
2
5
V
DIE TEMPERATURE SENSOR
Accuracy
±7
°C
Output Voltage at 25°C
1.5
V
Output Scale Factor
5
mV/°C
Output Voltage Range
0
3
V
INTERACTION & CROSSTALK
Crosstalk (VM)2
-0.01
0.01
% FSR
All channels in FIMV mode, measure the voltage for one
channel in the highest current force range, once when all
three other channels are at FI = 0mA and once when
they are at 2mA
Crosstalk (MI)2
-0.01
0.01
% FSR
All channels in FVMI mode, measure the current for one
channel in the lowest current measure range, once when
all three other channels are at FV = -10V and once when
they are at +10V
Crosstalk within a channel2
0.5
mV
All channels in FVMI mode, one channel at midscale,
measure the current for one channel in the lowest
current range, for a change in comparator or clamp DAC


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