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AD5362 Datasheet(PDF) 1 Page - Analog Devices

Part No. AD5362
Description  8-Channel, 16/14-Bit, Serial Input, Voltage-Output DAC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5362 Datasheet(HTML) 1 Page - Analog Devices

 
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8-Channel, 16/14-Bit,
Serial Input, Voltage-Output DAC
Preliminary Technical Data
AD5362/AD5363
Rev. P
rF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2006 Analog Devices, Inc. All rights reserved.
FEATURES
8-channel DAC in 52-LQFP and 56-LFCSP
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of -10 V to +10 V
Multiple output spans available
Temperature Monitoring Function
Channel Monitoring Multiplexer
GPIO Function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI compatible serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Instrumentation
Industrial Control System
PLC Analog I/O Cards
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Precision Medical Instruments
FUNCTIONAL BLOCK DIAGRAM
CONTROL
REGISTER
STATE
MACHINE
n
POWER-ON
RESET
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
AD5362/
AD5363
SERIAL
INTERFACE
8
BIN/2SCOMP
DAC 0
REGISTER
n
n
4
4
TO
MUX 2's
A/B SELECT
REGISTER
MUX
2
X2A REGISTER
X2B REGISTER
OFS1
REGISTER
14
14
DAC 0
OFFSET
DAC 1
BUFFER
DAC 3
REGISTER
n
n
MUX
2
X2A REGISTER
X2B REGISTER
DAC 3
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GROUP 1
LDAC
DVCC
VDD
VSS AGND DNGD
DAC 0
REGISTER
n
n
4
4
TO
MUX 2's
A/B SELECT
REGISTER
MUX
2
X2A REGISTER
X2B REGISTER
OFS0
REGISTER
14
14
DAC 0
OFFSET
DAC 0
BUFFER
GROUP 0
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DAC 3
REGISTER
n
n
MUX
2
X2A REGISTER
X2B REGISTER
DAC 3
BUFFER
AD5362, n = 16
AD5363, n = 14
GPIO
REGISTER
TEMP
SENSOR
TEMP_OUT
PEC
MON_IN0
MON_IN1
GPIO
MON_OUT
VOUT0 -
VOUT7
MUX
6
2
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND1
VREF0
SIGGND0
VOUT0
VOUT1
VOUT2
VOUT3
VREF1
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
5362-0001B
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
MREGISTER
CREGISTER
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
MREGISTER
CREGISTER
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
MREGISTER
CREGISTER
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
MREGISTER
CREGISTER
Figure 1.
AD5362/AD5363—Protected by U.S. Patent No. 5,969,657; other patents pending


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