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ADC08B3000 Datasheet(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. ADC08B3000
Description  High Performance, Low Power, 8-Bit, 3 GSPS A/D Converter with 4K Buffer
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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ADC08B3000 Datasheet(HTML) 1 Page - National Semiconductor (TI)

 
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ADC08B3000
High Performance, Low Power, 8-Bit, 3 GSPS A/D
Converter with 4K Buffer
General Description
Note: This product is currently in development. - ALL
specifications are design targets and are subject to
change.
The ADC08B3000 is a single, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 3.4 GSPS. Consuming
a typical 1.8 Watts at 3 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and
interpolating architecture, the fully differential comparator
design, the innovative design of the internal sample-and-
hold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters upto Nyquist, pro-
ducing a high 7.0 ENOB with a 748 MHz input signal and a
3 GHz sample rate while providing a 10
-18 B.E.R. 3 GSPS is
achieved through using a 1.5GHz clock. Output formatting is
offset binary. The device contains a 4K FIFO Capture Buffer
which is used to feed two 8 bit CMOS output busses at a rate
up to 200MHz.
The converter typically consumes less than 20 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40˚C
≤ T
A
≤ +85˚C) temperature range.
Features
n
Internal Sample-and-Hold
n
Single +1.9V ±0.1V Operation
n
Choice of SDR or DDR output clocking
n
Internal selectable 4K Data Buffer
n
Clock Phase Adjust for Multiple ADC Synchronization
n
Guaranteed No Missing Codes
n
Serial Interface for Extended Control
n
Fine Adjustment of Input Full-Scale Range and Offset
n
Duty Cycle Corrected Sample Clock
Key Specifications
n
Resolution
8 Bits
n
Max Conversion Rate
3 GSPS (min)
n
Bit Error Rate
10
-18 (typ)
n
ENOB @ 748 MHz Input
7.0 Bits (typ)
n
SNR @ 748 MHz
44 dB (typ)
n
Full Power Bandwidth
TBD
n
Power Consumption
— Operating
1.8 W (typ)
— Power Down Mode
20 mW (typ)
Applications
n
Ranging Applications
n
Test and measurement Applications
Block Diagram
20160153
ADVANCE INFORMATION
June 2006
© 2006 National Semiconductor Corporation
DS201601
www.national.com


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