 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADC08B3000 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
|
|
||||||||||||||||||||||||||||||
ADC08B3000 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
|
|
6 / 32 page 
Pin Descriptions and Equivalent Circuits (Continued) Pin Functions Pin No. Symbol Equivalent Circuit Description 115 FF Buffer Full Flag. This signal is asserted synchronous to the internal sampling clock when the capture buffer is full. If the WEN input remains asserted, the next CLK will cause an overflow, whereby the pointer will wrap around and begin overwriting the old data if the ASW bit is set to 0 in the Capture Buffer Control register. This signal is deasserted when a read cycle is initiated and the data buffer is no longer ’full’. 116 EF Buffer Empty Flag. This signal is asserted synchronous to the RCLK signal when the Capture Buffer is empty. It is deasserted when a write cycle is initiated and the data buffer is no longer ’empty’. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 V A Analog power supply pins. Bypass these pins to ground. 40, 51 ,62, 73, 88, 99, 110, 121 V DR Output Driver power supply pins. Bypass these pins to DR GND. 1, 6, 9, 12, 21, 24, 27, 41 GND Ground return for V A. 42, 53, 64, 74, 87, 97, 108, 119 DR GND Ground return for V DR. www.national.com 6 |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
