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ADC08B3000 Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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ADC08B3000 Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 32 page 
Pin Descriptions and Equivalent Circuits (Continued) Pin Functions Pin No. Symbol Equivalent Circuit Description 72 71 70 69 68 67 66 65 D2<0> D2<1> D2<2> D2<3> D2<4> D2<5> D2<6> D2<7> Digital Data Output 2. When the REN input is asserted and 2X8 Output Enable is set in the FIFO register, data from banks Da and Dc are read from the capture buffer and presented on this port synchronous with each rising edge of RCLK. When 2X8 Output Enable is not set in the FIFO register, data output 2 is high-Z. 75 DRDY2 Data Ready 2. DRDY is generated by RCLK and is synchronized to the output data. The use of this pin assists in eliminating the latency uncertainty between when RCLK transitions and when data transitions on the output 89 90 91 92 93 94 95 96 D1<0> D1<1> D1<2> D1<3> D1<4> D1<5> D1<6> D1<7> Digital Data Output 1. When the REN input is asserted, data is read from the capture buffer and presented on this port synchronous with each rising edge of RCLK. When 2X8 Output Eanble is set in the FIFO resgister, data from banks Db and Dd only are presented on this port. When REN is deasserted, this output holds the data from the previous read. When 2X8 Output Enable is not set in the FIFO register, port presents data from Da, Db, Dc, Dd banks. 86 DRDY1 Data Ready 1. DRDY is generated by RCLK and is synchronized to the output data. The use of this pin assists in eliminating the latency uncertainty between when RCLK transitions and when data transitions on the output 79 WENSYNC Synchronized WEN. The control input WEN is synchronized on-chip with the internal Sampling Clock and is provided at this output. 80 OR Out Of Range output. A logic high on this pin indicates that the differential input is out of range (outside the range ±300 mV or ±400 mV as defined by the FSR pin). This signal is asserted if the input signal has over ranged at any time during the data capture operation. This pin is cleared after the Capture Buffer is read or after asserting the RESET pin. 81 RESET A logic high at this input resets all Capture Buffer control logic in the chip. 82 RCLK Read Clock. Free running clock that is used to read data from the Capture Buffer. The parallel data on the data output port and the EF flag are asserted synchronous to this clock. www.national.com 5 |
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