Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ADC08B3000 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. ADC08B3000
Description  High Performance, Low Power, 8-Bit, 3 GSPS A/D Converter with 4K Buffer
Download  32 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo 

ADC08B3000 Datasheet(HTML) 4 Page - National Semiconductor (TI)

 
Zoom Inzoom in Zoom Outzoom out
 4 / 32 page
background image
Pin Descriptions and Equivalent Circuits (Continued)
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
18
19
V
IN+
V
IN
Analog signal inputs to the ADC. The differential full-scale
input range is 600 mV
P-P when the FSR pin is low, or 800
mV
P-P when the FSR pin is high.
7V
CMO
Common Mode Voltage. The voltage output at this pin is
required to be the common mode input voltage at V
IN+ and
V
IN− when d.c. coupling is used. This pin should be grounded
when a.c. coupling is used at the analog input. This pin is
capable of sourcing or sinking 100µA. See Section 2.2.
31
V
BG
Bandgap output voltage capable of 100 µA source/sink.
126
CalRun
Calibration Running indication. This pin is at a logic high
when calibration is running.
32
R
EXT
External bias resistor connection. Nominal value is 3.3k-Ohms
(±0.1%) to ground. See Section 1.1.1.
34
35
Tdiode_P
Tdiode_N
Temperature Diode Positive (Anode) and Negative (Cathode)
for die temperature measurements. See Section 2.6.2.
45
REN
Read Enable. A logic high on this input causes a byte of data
to be read from the Capture Buffer with each RCLK cycle.
This signal must not be asserted while the WEN is already
asserted. This signal may be asserted asynchronously as it is
internally synchronized with the internal sampling clock.
46
WEN
Write Enable. A logic high on this input causes a byte of data
to be written into the Capture Buffer with each sampling clock
cycle.This signal may be asserted asynchronously as it is
internally synchronized with the internal sampling clock.
www.national.com
4


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn