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ADUC7025 Datasheet(PDF) 11 Page - Analog Devices |
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ADUC7025 Datasheet(HTML) 11 Page - Analog Devices |
11 / 92 page ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 11 of 92 Table 4. I2C Timing in Fast Mode (400 kHz) Slave Parameter Description Min Max Master Typ Unit tL SCLOCK low pulse width1 200 1360 ns tH SCLOCK high pulse width1 100 1140 ns tSHD Start condition hold time 300 251350 ns tDSU Data setup time 100 740 ns tDHD Data hold time 50 400 ns tRSU Setup time for repeated start 100 12.51350 ns tPSU Stop condition setup time 100 400 ns tBUF Bus-free time between a stop condition and a start condition 1.3 μs tR Rise time for both CLOCK and SDATA 100 300 200 ns tF Fall time for both CLOCK and SDATA 60 100 20 ns tSUP Pulse width of spike suppressed 50 ns 1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. SDATA (I/O) tBUF MSB LSB ACK MSB 1 9 8 2–7 1 SCLK (I) PS STOP CONDITION START CONDITION S(R) REPEATED START tSUP tR tF tF tR tH tL tSUP tDSU tDHD tRSU tDHD tDSU tSHD tPSU Figure 5. I2C Compatible Interface Timing |
Similar Part No. - ADUC7025 |
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Similar Description - ADUC7025 |
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