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ADSP-1981BL Datasheet(PDF) 5 Page - Analog Devices

Part No. ADSP-1981BL
Description  AC 97 SoundMAX Codec
Download  32 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-1981BL Datasheet(HTML) 5 Page - Analog Devices

 
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AD1981BL
Rev. A | Page 5 of 32
Parameter
Min
Typ
Max
Unit
Low Level Output Voltage (VOL), IOL = 2 mA
0.1 × DVDD
V
Input Leakage Current
−10
+10
µA
Output Leakage Current
−10
+10
µA
POWER SUPPLY
Power Supply Range (AVDD and DVDD)
3.0
3.47
V
Power Dissipation
2.87
mW
Analog Supply Current—3.3 V (AVDD)
39
mA
Digital Supply Current—3.3 V (DVDD)
48
mA
Power Supply Rejection (100 mV p-p Signal at 1 kHz)1
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
40
dB
CLOCK SPECIFICATIONS1
Input Clock Frequency
24.576
MHz
Recommended Clock Duty Cycle
40
50
60
%
1 Guaranteed but not tested.
2 Measurements reflect main ADC.
POWER-DOWN STATES
Values presented with VREFOUT not loaded.
Table 3.
Parameter
Set Bits
DVDD Typ
AVDD Typ
Unit
Fully Active
No Bits Value
47.76
38.9
mA
ADC
PR0
40.1
34.39
mA
DAC
PR1
32.8
26.3
mA
ADC + DAC
PR1, PR0
13.2
20.55
mA
Mixer
PR2
47.7
19.39
mA
ADC + Mixer
PR2, PR0
40
14.86
mA
DAC + Mixer
PR2, PR1
32.77
6.39
mA
ADC + DAC + Mixer
PR2, PR1, PR0
13.9
1.15
mA
Standby
PR5, PR4, PR3, PR2, PR1, PR0
0
0
mA
Headphone Standby
PR6
47.7
32
mA
TIMING PARAMETERS
Guaranteed over operating temperature range.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
RESET Active Low Pulse Width
tRST_LOW
1.0
ms
RESET Inactive to BIT_CLK Start-Up Delay
tRST2CLK
162.8
ns
SYNC Active High Pulse Width
tSYNC_HIGH
1.3
µs
SYNC Low Pulse Width
tSYNC_LOW
19.5
µs
SYNC Inactive to BIT_CLK Start-Up Delay
tSYNC2CLK
162.8
ns
BIT_CLK Frequency
12.288
MHz
BIT_CLK Frequency Accuracy
±1
ppm
BIT_CLK Period
tCLK_PERIOD
81.4
ns
BIT_CLK Output Jitter1, ,2 3
750
2000
ps
BIT_CLK High Pulse Width
tCLK_HIGH
32.56
42
48.84
ns
BIT_CLK Low Pulse Width
tCLK_LOW
32.56
38
ns
SYNC Frequency
48.0
kHz


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