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ADP3118 Datasheet(PDF) 3 Page - Analog Devices |
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ADP3118 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 16 page  ADP3118 Rev. 0 | Page 3 of 16 SPECIFICATIONS1 VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ Max Unit PWM INPUT Input Voltage High 2.0 V Input Voltage Low 0.8 V Input Current −1 +1 µA Hysteresis 90 250 mV OD INPUT Input Voltage High 2.0 V Input Voltage Low 0.8 V Input Current −1 +1 µA Hysteresis 90 250 mV Propagation Delay Times2 tpdlOD See Figure 3 20 35 ns tpdhOD See Figure 3 40 55 ns HIGH-SIDE DRIVER Output Resistance, Sourcing Current BST − SW = 12 V 2.2 3.5 Ω Output Resistance, Sinking Current BST − SW = 12 V 1.0 2.5 Ω Output Resistance, Unbiased BST − SW = 0 V 10 kΩ Transition Times trDRVH BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 25 40 ns tfDRVH BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 20 30 ns Propagation Delay Times2 tpdhDRVH BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 25 40 ns tpdlDRVH BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 25 35 ns SW Pull-Down Resistance SW to PGND 10 kΩ LOW-SIDE DRIVER Output Resistance, Sourcing Current 2.0 3.2 Ω Output Resistance, Sinking Current 1.0 2.5 Ω Output Resistance, Unbiased VCC = PGND 10 kΩ Transition Times trDRVL CLOAD = 3 nF, see Figure 4 20 35 ns tfDRVL CLOAD = 3 nF, see Figure 4 16 30 ns Propagation Delay Times2 tpdhDRVL CLOAD = 3 nF, see Figure 4 12 35 ns tpdlDRVL CLOAD = 3 nF, see Figure 4 30 45 ns Timeout Delay SW = 5 V 110 190 ns SW = PGND 95 150 ns SUPPLY Supply Voltage Range VCC 4.15 13.2 V Supply Current ISYS BST = 12 V, IN = 0 V 2 5 mA UVLO Voltage VCC rising 1.5 3.0 V Hysteresis 350 mV 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. 2 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low. |
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