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ADP3118 Datasheet(PDF) 5 Page - Analog Devices

Part No. ADP3118
Description  Dual Bootstrapped 12 V MOSFET Driver with Output Disable
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP3118 Datasheet(HTML) 5 Page - Analog Devices

 
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ADP3118
Rev. 0 | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BST
1
IN
2
OD
3
VCC
4
DRVH
8
SW
7
PGND
6
DRVL
5
ADP3118
TOP VIEW
(Not to Scale)
Figure 2. 8-Lead SOIC Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.
2
IN
Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.
3
OD
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
4
VCC
Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5
DRVL
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6
PGND
Power Ground. Should be closely connected to the source of the lower MOSFET.
7
SW
This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return
for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the
lower MOSFET until the voltage is below ~1 V.
8
DRVH
Buck Drive. Output drive for the upper (buck) MOSFET.


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