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ADP1710 Datasheet(PDF) 3 Page - Analog Devices

Part No. ADP1710
Description  150 mA, Low Dropout, CMOS Linear Regulator
Download  16 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP1710 Datasheet(HTML) 3 Page - Analog Devices

 
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ADP1710/ADP1711
Rev. 0 | Page 3 of 16
SPECIFICATIONS
VIN = (VOUT + 0.5 V) or 2.5 V (whichever is greater), IOUT = 1 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT VOLTAGE RANGE
VIN
TJ = –40°C to +125°C
2.5
5.5
V
OPERATING SUPPLY CURRENT
IGND
IOUT = 0 μA
35
μA
IOUT = 0 μA, TJ = –40°C to +125°C
50
μA
IOUT = 100 μA
40
μA
IOUT = 100 μA, TJ = –40°C to +125°C
80
μA
IOUT = 100 mA
665
μA
IOUT = 100 mA, TJ = –40°C to +125°C
860
μA
IOUT = 150 mA
1
mA
IOUT = 150 mA, TJ = –40°C to +125°C
1.3
mA
SHUTDOWN CURRENT
IGND-SD
EN = GND
0.1
μA
EN = GND, TJ = –40°C to +125°C
1.0
μA
FIXED OUTPUT VOLTAGE ACCURACY
VOUT
IOUT = 1 mA
–1
+1
%
(ADP1710 AND ADP1711)
100 μA < IOUT < 150 mA, TJ = –40°C to +125°C
–2
+2
%
ADJUSTABLE OUTPUT VOLTAGE
VOUT
IOUT = 1 mA
0.792
0.8
0.808
V
ACCURACY (ADP1710 ADJUSTABLE)1
100 μA < IOUT < 150 mA, TJ = –40°C to +125°C
0.784
0.816
V
LINE REGULATION
∆VOUT/∆VIN
VIN = (VOUT + 0.5 V) to 5.5 V, TJ = –40°C to +125°C
–0.1
+0.1
%/ V
LOAD REGULATION2
∆VOUT/∆IOUT
IOUT = 10 mA to 150 mA
0.002
%/mA
IOUT = 10 mA to 150 mA, TJ = –40°C to +125°C
0.004
%/mA
DROPOUT VOLTAGE3
VDROPOUT
IOUT = 100 mA, VOUT ≥ 3.0 V
100
mV
IOUT = 100 mA, VOUT ≥ 3.0 V, TJ = –40°C to +125°C
175
mV
IOUT = 150 mA, VOUT ≥ 3.0 V
150
mV
IOUT = 150 mA, VOUT ≥ 3.0 V, TJ = –40°C to +125°C
250
mV
IOUT = 100 mA, 2.5 V ≤ VOUT < 3.0 V
120
mV
IOUT = 100 mA, 2.5 V ≤ VOUT < 3.0 V, TJ = –40°C to +125°C
200
mV
IOUT = 150 mA, 2.5 V ≤ VOUT < 3.0 V
180
mV
IOUT = 150 mA, 2.5 V ≤ VOUT < 3.0 V, TJ = –40°C to +125°C
300
mV
START-UP TIME4
TSTART-UP
ADP1710
80
μs
ADP1711
With 10 nF bypass capacitor
100
μs
CURRENT LIMIT THRESHOLD5
ILIMIT
180
270
360
mA
THERMAL SHUTDOWN THRESHOLD
TSSD
TJ rising
150
°C
THERMAL SHUTDOWN HYSTERESIS
TSSD-HYS
15
°C
UVLO ACTIVE THRESHOLD
UVLOACTIVE
VIN falling
1.95
V
UVLO INACTIVE THRESHOLD
UVLOINACTIVE
VIN rising
2.45
V
UVLO HYSTERESIS
UVLOHYS
250
mV
EN INPUT LOGIC HIGH
VIH
2.5 V ≤ VIN ≤ 5.5 V
1.8
V
EN INPUT LOGIC LOW
VIL
2.5 V ≤ VIN ≤ 5.5 V
0.4
V
EN INPUT LEAKAGE CURRENT
VI-LEAKAGE
EN = IN or GND
0.1
1
μA
ADJ INPUT BIAS CURRENT
(ADP1710 ADJUSTABLE)
ADJI-BIAS
30
100
nA
OUTPUT NOISE
OUTNOISE
ADP1710
10 Hz to 100 kHz, VOUT = 3.3 V
330
μVrms
ADP1711
10 Hz to 100 kHz, VOUT = 0.75 V, with 10 nF bypass capacitor
40
μVrms
POWER SUPPLY REJECTION RATIO
PSRR
ADP1710
1 kHz, VOUT = 3.3 V
58
dB
ADP1711
1 kHz, VOUT = 0.75 V, with 10 nF bypass capacitor
69
dB
1 Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances
of resistors used.
2 Based on an end-point calculation using 10 mA and 150 mA loads. See Figure 8 for typical load regulation performance for loads less than 10 mA.
3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.5 V.
4 Start-up time is defined as the time between the rising edge of EN to OUT being at 90% of its nominal value.
5 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.


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