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NB2304AI1DG Datasheet(PDF) 7 Page - ON Semiconductor |
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NB2304AI1DG Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 10 page NB2304A http://onsemi.com 7 Zero Delay and Skew Control For applications requiring zero input−output delay, all outputs must be equally loaded. Figure 3. REF Input to CLKA/CLKB Delay vs. Difference in Loading between FBK Pin and CLKA/CLKB Pins 1500 1000 500 0 −500 −1000 −1500 −30 −25 −20 −15 −10 −5 0 5 10 1520 2530 OUTPUT LOAD DIFFERENCE: FBK LOAD − CLKA/CLKB LOAD (pF) To close the feedback loop of the NB2304A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in Figure 3. For applications requiring zero input−output delay, all outputs including the one providing feedback should be equally loaded. If input−output delay adjustments are required, use Figure 3 to calculate loading differences between the feedback output and remaining outputs. For zero output−output skew, be sure to load outputs equally. SWITCHING WAVEFORMS Figure 4. Duty Cycle Timing 1.4 V 1.4 V 1.4 V t1 t2 Figure 5. All Outputs Rise/Fall Time t3 OUTPUT 2.0 V 0.8 V t4 2.0 V 0.8 V 3.3 V 0 V 1.4 V 1.4 V t5 Figure 6. Output − Output Skew OUTPUT OUTPUT t6 INPUT OUTPUT Figure 7. Input − Output Propagation Delay VDD 2 VDD 2 Figure 8. Device − Device Skew t7 FBK_Device 1 VDD 2 VDD 2 FBK_Device 2 |
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