© Semiconductor Components Industries, LLC, 2006

June, 2006 − Rev. 3

1

Publication Order Number:

NB4N527S/D

NB4N527S

3.3V, 2.5Gb/s Dual

AnyLevel™ to LVDS

Receiver/Driver/Buffer/

Translator with Internal

Input Termination

NB4N527S is a clock or data Receiver/Driver/Buffer/Translator

HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the

distance, noise immunity of the system design, and transmission line

media, this device will receive, drive or translate data or clock signals

up to 2.5 Gb/s or 1.5 GHz, respectively.

The NB4N527S has a wide input common mode range of

termination resistors is ideal for translating differential or

single−ended data or clock signals to 350 mV typical LVDS output

levels without use of any additional external components (Figure 6).

The device is offered in a small 3 mm x 3 mm QFN−16 package.

NB4N527S is targeted for data, wireless and telecom applications as

well as high speed logic interface where jitter and package size are

main requirements. Application notes, models, and support

documentation are available on www.onsemi.com.

TIME (58 ps/div)

Figure 2. Typical Output Waveform at 2.488 Gb/s with

Device DDJ = 10 ps

A

= Assembly Location

L

= Wafer Lot

Y

= Year

W

= Work Week

G

= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAM*

QFN−16

MN SUFFIX

CASE 485G

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

16

NB4N

527S

ALYW

G

G

1

Q0

Q0

Figure 1. Functional Block Diagram

VTD0

D0

Q1

Q1

D0

50

W*

D1

D1

VTD0

50

W*

50

W*

50

W*

VTD1

VTD1

1

(Note: Microdot may be in either location)