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NB4N527S Datasheet(PDF) 2 Page - ON Semiconductor

Part No. NB4N527S
Description  3.3V, 2.5Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB4N527S Datasheet(HTML) 2 Page - ON Semiconductor

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NB4N527S
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Figure 3. Pin Configuration (Top View)
GND
NC
NC
VCC
VTD0 D0
D0 VTD0
Q0
Q0
Q1
Q1
VTD1
D1
D1
VTD1
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB4N527S
Exposed Pad (EP)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTD1
Internal 50
W termination pin for D1. (RTIN)
2
D1
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Noninverted differential clock/data D1 input (Note 1).
3
D1
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Inverted differential clock/data D1 input (Note 1).
4
VTD1
Internal 50
W termination pin for D1. (RTIN)
5
GND
0 V. Ground.
6, 7
NC
No connect.
8
VCC
Positive Supply Voltage.
9
Q1
LVDS Output
Inverted D1 output. Typically loaded with 100
W receiver termination
resistor across differential pair.
10
Q1
LVDS Output
Noninverted D1 output. Typically loaded with 100
W receiver termination
resistor across differential pair.
11
Q0
LVDS Output
Inverted D0 output. Typically loaded with 100
W receiver termination
resistor across differential pair.
12
Q0
LVDS Output
Noninverted D0 output. Typically loaded with 100
W receiver termination
resistor across differential pair.
13
VTD0
Internal 50
W termination pin for D0.
14
D0
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Noninverted differential clock/data D0 input (Note 1).
15
D0
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Inverted differential clock/data D0 input (Note 1).
16
VTD0
Internal 50
W termination pin for D0.
EP
Exposed pad. EP on the package bottom is thermally connected to the die
improved heat transfer out of package. The pad is not electrically connected
to the die, but is recommended to be soldered to GND on the PCB.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self−oscillation.


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