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NB4N527S Datasheet(PDF) 1 Page - ON Semiconductor

Part No. NB4N527S
Description  3.3V, 2.5Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB4N527S Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 3
1
Publication Order Number:
NB4N527S/D
NB4N527S
3.3V, 2.5Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator with Internal
Input Termination
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevelTM input signal (LVPECL, CML,
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 2.5 Gb/s or 1.5 GHz, respectively.
The NB4N527S has a wide input common mode range of
GND + 50 mV to VCC − 50 mV combined with two 50 W internal
termination resistors is ideal for translating differential or
single−ended data or clock signals to 350 mV typical LVDS output
levels without use of any additional external components (Figure 6).
The device is offered in a small 3 mm x 3 mm QFN−16 package.
NB4N527S is targeted for data, wireless and telecom applications as
well as high speed logic interface where jitter and package size are
main requirements. Application notes, models, and support
documentation are available on www.onsemi.com.
Maximum Input Clock Frequency up to 1.5 GHz
Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)
470 ps Maximum Propagation Delay\
1 ps Maximum RMS Jitter
140 ps Maximum Rise/Fall Times
Single Power Supply; VCC = 3.3 V $10%
Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
Internal 50 W Termination Resistor per Input Pin
GND + 50 mV to VCC − 50 mV VCMR Range
Pb−Free Packages are Available
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
Device DDJ = 10 ps
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN−16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
16
NB4N
527S
ALYW
G
G
1
Q0
Q0
Figure 1. Functional Block Diagram
VTD0
D0
Q1
Q1
D0
50
W*
D1
D1
VTD0
50
W*
50
W*
50
W*
VTD1
VTD1
1
*RTIN
(Note: Microdot may be in either location)


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