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NB4N441 Datasheet(PDF) 6 Page - ON Semiconductor

Part No. NB4N441
Description  3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Differential LVPECL Output
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NB4N441 Datasheet(HTML) 6 Page - ON Semiconductor

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NB4N441
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Table 6. DC CHARACTERISTICS VCC = 3.135 V to 3.465 V, GND = 0 V, TA = −40°C to +85°C
Symbol
Characteristic
Min
Typ
Max
Unit
ICC
Power Supply Current (Inputs and Outputs Loaded)
50
60
70
mA
ICCPLL
PLL Power Supply Current
10
20
mA
VOH
LVPECL Output HIGH Voltage (Notes 4 and 5)
VCC = 3.3 V
VCC – 1145
2155
VCC − 1030
2270
VCC – 895
2405
mV
VOL
LVPECL Output LOW Voltage (Notes 4 and 5)
VCC = 3.3 V
VCC – 1945
1355
VCC − 1760
1540
VCC – 1695
1605
mV
VOHTTL
Output HIGH Voltage (LOCKED Pin)
IOH = −0.8 mA
2.5
VCC
V
VOLTTL
Output LOW Voltage (LOCKED Pin)
GND
0.4
V
VIH
Input HIGH Voltage (LVTTL/LVCMOS)
2.0
VCC
V
VIL
Input LOW Voltage (LVTTL/LVCMOS)
GND
0.8
V
IIH
Input HIGH Current
VIN = 2.7V, VCCmax
VIN = VCC, VCCmax
6
20
16
45
mA
mA
IIL
Input LOW Current
VIN = 0.5V, VCCmax
10
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL Outputs loaded with 50 W termination resistors to VTT = VCC – 2.0 V for proper operation.
5. LVPECL Output parameters vary 1:1 with VCC.
Table 7. AC CHARACTERISTICS VCC = 3.135 V to 3.465 V, GND = 0 V, TA = −40°C to +85°C (Note 6)
Symbol
Characteristic
Min
Typ
Max
Unit
fIN
Crystal Input Frequency
External CLOCK Input Frequency (Pin 8)
SCLOCK
10
27
27
28
50
10
MHz
VOUTPP
Output Voltage Amplitude
600
800
mV
fVCO
VCO Frequency Range
400
850
MHz
fCLKOUT
Output Clock Frequency Range
12.5
425
MHz
tR/tF_IN
Input Clock Rise and Fall Time (CLK, Pin 8) (Note 7)
10
ns
tLOCK
Maximum PLL Lock Time
0.5
5
ms
DCO
Output CLOCK Duty Cycle (Differential Configuration)
48
52
%
tJITTER(pd)
Period Jitter (RMS, 1s, 10,000 Cycles) (Notes 8 and 9)
3.5
6.5
ps
tJITTER(pd)
Period Jitter (Peak−to−Peak, 10,000 Cycles) (Note 9)
25
40
ps
ts
Setup Time
SDATA to SCLOCK
SCLOCK to SLOAD
20
20
ns
ns
th
Hold Time
SDATA to SCLOCK
SCLOCK to SLOAD
20
20
ns
ns
tpwmin
Minimum Pulse Width SLOAD
20
ns
tr, tf
Output Rise/Fall Times (Note 7) CLKOUT / CLKOUT
175
300
425
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. LVPECL Outputs loaded with 50 W to VCC − 2.0 V.
7. Measured 20% to 80%
8. Additive RMS jitter with 50% duty cycle input clock signal at 27.000 MHz; fOUT = 155 MHz.
9. fOUT = 155 MHz. Protocol 13.28125 MHz will have typical period jitter (RMS) of 14 ps and a typical cycle−to−cycle jitter of 95 ps.


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