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NB4L858M Datasheet(PDF) 3 Page - ON Semiconductor

Part No. NB4L858M
Description  2.5V/3.3V, 3 GHz Dual Differential Clock/Data 2x2 Crosspoint Switch with CML Output and Internal Termination
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB4L858M Datasheet(HTML) 3 Page - ON Semiconductor

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NB4L858M
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Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
DB1
LVPECL, CML Input
Channel B1 positive signal input.
2
VTDB1
Internal 100
W center−tapped termination pin for channel B1.
3
DB1
LVPECL, CML Input
Channel B1 negative signal input.
4
SELB0
LVTTL / LVCMOS
Channel B0 Output Select. See Table 1.
5
DB0
LVPECL, CML Input
Channel B0 positive signal input.
6
VTDB0
Internal 100
W center−tapped termination pin for channel B0.
7
DB0
LVPECL, CML Input
Channel B0 negative signal input.
8
SELB1
LVTTL / LVCMOS
Channel B1 output select. See Table 1.
9,24
GND
Supply ground. All GND pins must be externally connected to power supply to
guarantee proper operation.
10, 13, 16, 17, 20, 23
VCC
Positive Supply. All VCC pins must be externally connected to power supply to
guarantee proper operation.
11
QB0
CML Output
Channel B0 negative signal output. Typically terminated with 50
W resistor to
VCC.
12
QB0
CML Output
Channel B0 positive signal output. Typically terminated with 50
W resistor to
VCC
14
QB1
CML Output
Channel B1 negative signal output. Typically terminated with 50
W resistor to
VCC.
15
QB1
CML Output
Channel B1 positive signal output. Typically terminated with 50
W resistor to
VCC.
18
QA1
CML Output
Channel A1 negative signal output. Typically terminated with 50
W resistor to
VCC.
19
QA1
CML Output
Channel A1 positive signal output. Typically terminated with 50
W resistor to
VCC.
21
QA0
CML Output
Channel A0 negative signal output. Typically terminated with 50
W resistor to
VCC.
22
QA0
CML Output
Channel A0 positive signal output. Typically terminated with 50
W resistor to
VCC.
25
DA0
LVPECL, CML Input
Channel A0 positive signal input.
26
VTDA0
Internal 100
W center−tapped termination pin for channel A0.
27
DA0
LVPECL, CML Input
Channel A0 negative signal input.
28
SELA1
LVTTL
Channel A1 output select. See Table 1.
29
DA1
LVPECL, CML Input
Channel A1 positive signal input.
30
VTDA1
Internal 100
W center−tapped termination pin for channel A1.
31
DA1
LVPECL, CML Input
Channel A1 negative signal input.
32
SELA0
LVTTL
Channel A0 output select. See Table 1.


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