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ADN2818ACP Datasheet(PDF) 22 Page - Analog Devices |
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ADN2818ACP Datasheet(HTML) 22 Page - Analog Devices |
22 / 35 page ADN2817/ADN2818 Preliminary Technical Data Rev. PrA | Page 22 of 35 peak-to-peak differential amplitude of greater than 100 mV (for example, LVPECL or LVDS) or a standard single-ended low voltage TTL input, providing maximum system flexibility. Phase noise and duty cycle of the reference clock are not critical and 100 ppm accuracy is sufficient. REFCLKP REFCLKN ADN2817/18 Buffer VCC/2 100k 100k 10 11 Figure 21. Differential REFCLK Configuration REFCLKP REFCLKN ADN2817/18 Buffer VCC/2 100k 100k x CLK OSC VCC OUT 10 11 Figure 22. Single-Ended REFCLK Configuration REFCLKP REFCLKN ADN2817/18 Buffer VCC/2 100k 100k VCC NC 10 11 Figure 23. No REFCLK Configuration The two uses of the reference clock are mutually exclusive. The reference clock can be used either as an acquisition aid for the ADN2817/ADN2818 to lock onto data, or to measure the frequency of the incoming data to within 0.01%. (There is the capability to measure the data rate to approximately ±10% without the use of a reference clock.) The modes are mutually exclusive, because, in the first use, the user knows exactly what the data rate is and wants to force the part to lock onto only that data rate; in the second use, the user does not know what the data rate is and wants to measure it. Lock to reference mode is enabled by writing a 1 to I2C Register Bit CTRLA[0]. Fine data rate readback mode is enabled by writing a 1 to I2C Register Bit CTRLA[1]. Writing a 1 to both of these bits at the same time causes an indeterminate state and is not supported. Using the Reference Clock to Lock onto Data In this mode, the ADN2817/ADN2818 locks onto a frequency derived from the reference clock according to the following equation: Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6] The user must know exactly what the data rate is, and provide a reference clock that is a function of this rate. The ADN2817/ADN2818 can still be used as a continuous rate device in this configuration, provided that the user has the ability to provide a reference clock that has a variable frequency (see Application Note AN-632). The reference clock can be anywhere between 12.3 MHz and 200 MHz. By default, the ADN2817/ADN2818 expects a reference clock of between 12.3 MHz and 25 MHz. If it is between 25 MHz and 50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user needs to configure the ADN2817/ADN2818 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Table 12. CTRLA Settings CTRLA[7:6] Range (MHz) CTRLA[5:2] Ratio 00 12.3 to 25 0000 1 01 25 to 50 0001 2 10 50 to 100 n 2n 11 100 to 200 1000 256 The user can specify a fixed integer multiple of the reference clock to lock onto using CTRLA[5:2], where CTRLA should be set to the data rate/DIV_FREF, where DIV_FREF represents the divided-down reference referred to the 12.3 MHz to 25 MHz band. For example, if the reference clock frequency was 38.88 MHz and the input data rate was 622.08 Mb/s, then CTRLA[7:6] would be set to [01] to give a divided-down reference clock of 19.44 MHz. CTRLA[5:2] would be set to [0101], that is, 5, because 622.08 Mb/s/19.44 MHz = 25 In this mode, if the ADN2817/ADN2818 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. While the ADN2817/ADN2818 is operating in lock to reference mode, if the user ever changes the reference frequency, the FREF range (CTRLA[7:6]), or the FREF ratio (CTRLA[5:2]), this must be followed by writing a 0 to 1 transition into the CTRLA[0] bit to initiate a new lock to reference command. Using the Reference Clock to Measure Data Frequency The user can also provide a reference clock to measure the recovered data frequency. In this case, the user provides a reference clock, and the ADN2817/ADN2818 compares the frequency of the incoming data to the incoming reference clock |
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