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NB4L16M Datasheet(PDF) 2 Page - ON Semiconductor

Part No. NB4L16M
Description  2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator with Internal Termination
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NB4L16M Datasheet(HTML) 2 Page - ON Semiconductor

 
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NB4L16M
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2
Figure 2. Pin Configuration (Top View)
VCC NC VEE VEE
VCC VBB VEE VEE
VCC
Q
Q
VCC
VTD
D
D
VTD
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB4L16M
Exposed Pad (EP)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTD
Internal 50 W termination pin. See Table 4 (Note 1).
2
D
LVPECL, CML, HSTL,
LVCMOS, LVDS, LVTTL Input
Inverted differential input. Internal 36.5 kW to VCC and 73 kW to VEE
(Note 1).
3
D
LVPECL, CML, HSTL,
LVCMOS, LVDS, LVTTL Input
Noninverted differential input. Internal 73 kW to VCC and 36.5 kW to VEE
(Note 1).
4
VTD
Internal 50 W termination pin. See Table 4. (Note 1)
15
VBB
Internally generated reference voltage supply.
6
NC
No Connect pin. The No Connect (NC) pin is electrically connected to the
die and MUST be left open.
10
Q
CML Output
Noninverted differential output. Typically receiver terminated with 50 W
resistor to VCC.
11
Q
CML Output
Inverted differential output. Typically receiver terminated with 50 W resistor
to VCC.
7, 8, 13, 14
VEE
Negative supply voltage
5, 9, 12, 16
VCC
Positive supply voltage
EP
Exposed pad (EP). EP on the package bottom is thermally connected to the
die for improved heat transfer out of the package. The pad is not electrically
connected to the die, but is recommended to be soldered to VEE on the
PC Board.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage and if no signal
is applied on D/D input then the device will be susceptible to self−oscillation.


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