NB3N3011

http://onsemi.com

5

APPLICATION INFORMATION

Power Supply Filtering

The NB3N3011 is a mixed analog/digital product, and as

such, it exhibits some sensitivities that would not necessarily

be seen on a fully digital product. Analog circuitry is

naturally susceptible to random noise, especially if this noise

is seen on the power supply pins. The NB3N3011 also

generates sub−nanosecond output edge rates, and therefore,

a good power supply bypassing scheme is a must.

The NB3N3011 provides separate power supplies for the

simplest form of noise isolation is a power supply filter on

Figure 8 illustrates a typical power supply filter scheme.

The parallel capacitor combination shown ensures that a low

impedance path to ground exists for frequencies well above

the bandwidth of the PLL.

The purpose of this design technique is to try and isolate

the high switching noise of the digital outputs from the

relatively sensitive internal analog phase−locked loop. The

power supply filter and bypass schemes discussed in this

section should be adequate to eliminate power supply

noise−related problems in most designs.

Crystal Oscillator Input Interface

The NB3N3011 features an integrated crystal oscillator to

minimize system implementation costs. The oscillator

circuit is a parallel resonant circuit and thus, for optimum

performance, a parallel resonant crystal should be used.

As the oscillator is somewhat sensitive to loading on its

inputs, the user is advised to mount the crystal as close to the

NB3N3011 as possible to avoid any board level parasitics.

Surface mount crystals are recommended, but not required.

Figure 9 illustrates a parallel resonant crystal with its

associated load capacitors. The capacitor values shown were

determined using a 26.5625 MHz, 18 pF parallel resonant

crystal and were chosen to minimize the ppm error.

Capacitor values can be adjusted slightly for different board

layouts to optimize accuracy.

Figure 8. Power Supply Filtering

3.3 V

0.01 mF

0.01 mF

10 mF

10 W

Figure 9. Crystal Input Interface

C1

33 pF

X1

18 pF

C2

27 pF

Parallel Crystal

APPLICATION SCHEMATIC

Figure 10 shows a schematic example of the NB3N3011.

An example of LVPECL termination is shown in this

schematic. Additional LVPECL termination approaches are

shown in the AND8020 Application Note. In this example,

an 18 pF parallel resonant 26.5625MHz crystal is used for

generating 106.25 MHz output frequency. The C1 = 27 pF

and C2 = 33 pF are recommended for frequency accuracy.

For different board layout, the C1 and C2 values may be

slightly adjusted for optimizing frequency accuracy.

Figure 10. Typical Application Schematic

R2

10

33 pF

R6

82.5

+

−

U1

1

2

3

4

8

7

6

5

R3

133

X1

Q

C5

C4

C1

27 pF

R5

133

R4

82.5

18 pF

C3

0.01 mF

10 mF

C2

0.1 m

Q

NC

Q

Q