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NB3N502 Datasheet(PDF) 4 Page - ON Semiconductor

Part No. NB3N502
Description  14 MHz to 190 MHz PLL Clock Multiplier
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NB3N502 Datasheet(HTML) 4 Page - ON Semiconductor

   
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NB3N502
http://onsemi.com
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APPLICATIONS INFORMATION
High Frequency CMOS/TTL Oscillators
The NB3N502, along with a low frequency fundamental
mode crystal, can build a high frequency CMOS/TTL output
oscillator. For example, a 20 MHz crystal connected to the
NB3N502 with the 5X output selected (S1 = L, S0 = H)
produces a 100 MHz CMOS/TTL output clock.
External Components
Decoupling Instructions
In order to isolate the NB3N502 from system power
supply, noise de−coupling is required. The 0.01
mF
decoupling capacitor has to be connected between VDD and
GND on pins 2 and 3. It is recommended to place
de−coupling capacitors as close as possible to the NB3N502
device to minimize lead inductance. Control input pins can
be connected to device pins VDD or GND, or to the VDD and
GND planes on the board.
Series Termination Resistor Recommendation
A 33
W series terminating resistor can be used on the
CLKOUT pin.
Crystal Load Capacitors Selection Guide
The total on−chip capacitance is approximately 12 pF per
pin (CIN1 and CIN2). A parallel resonant, fundamental mode
crystal should be used.
The device crystal connections should include pads for
small capacitors from X1/CLK to ground and from X2 to
ground. These capacitors, CL1 and CL2, are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance (CLOAD (crystal)).
Because load capacitance can only be increased in this
trimming process, it is important to keep stray capacitance
to a minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal load capacitors, if
needed, must be connected from each of the pins X1 and X2
to ground. The load capacitance of the crystal (CLOAD
(crystal)) must be matched by total load capacitance of the
oscillator circuitry network, CINX, CSX and CLX, as seen by
the crystal (see Figure 3 and equations below).
R
CIN1
12 pF
CIN2
12 pF
G
Internal
to Device
X2
X1/CLK
CS1
CS2
CL1
CL2
Crystal
CLOAD1 = CIN1 + CS1 + CL1 [Total capacitance on X1/CLK]
CLOAD2 = CIN2 + CS2 + CL2 [Total capacitance on X2]
CIN1 [ CIN2 [ 12 pF (Typ) [Internal capacitance]
CS1 [ CS2 [ 5 pF (Typ) [External PCB stray capacitance]
CLOAD1,2 = 2 S CLOAD (Crystal)
CL2 = CLOAD2 − CIN2 − CS2 [External load capacitance on X2]
CL1 = CLOAD1 − CIN1 − CS1 [External load capacitance on X1/CLK]
Example 1: Equal stray capacitance on PCB
CLOAD (Crystal) = 18 pF (Specified by the crystal manufacturer)
CLOAD1 = CLOAD2 = 36 pF
CIN1 = CIN2 = 12 pF
CS1 = CS2 = 6 pF
CL1 = 36 − 12 − 6 = 18 pF
CL2 = 36 − 12 − 6 = 18 pF
Example 2: Different stray capacitance on PCB trace X1/CLK vs. X2
CLOAD (Crystal) = 18 pF
CLOAD1 = CLOAD2 = 36 pF
CIN1 = CIN2 = 12 pF
CS1 = 4 pF & CS2 = 8 pF
CL1 = 36 − 12 − 4 = 20 pF
CL2 = 36 − 12 − 8 = 16 pF
Figure 3. Using a Crystal as Reference Clock


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