MC100LVEL34

http://onsemi.com

2

Q0

Q1

Q2

15

16

14

13

12

11

10

2

1

3

4

5

6

7

9

8

EN

NC

CLK

CLK

MR

D

Q

R

Q

R

÷2

Q

R

÷4

Q

R

÷8

CLK*, CLK**

ECL Diff Clock Inputs

EN*

ECL Sync Enable

MR*

ECL Master Reset

Q0, Q0

ECL Diff ÷2 Outputs

Q1, Q1

ECL Diff ÷4 Outputs

Q2, Q2

ECL Diff ÷8 Outputs

Reference Voltage Output

Positive Supply

Negative Supply

NC

No Connect

Table 1. PIN DESCRIPTION

CLK

Z

ZZ

X

EN

L

H

X

MR

L

L

H

Table 2. FUNCTION TABLE

Z = Low-to-High Transition

ZZ = High-to-Low Transition

PIN

FUNCTION

to Power Supply to guarantee proper operation.

FUNCTION

Divide

Q0

Q1

Q2

* Pins will default LOW when left open.

Figure 1. 16−Lead Pinout (Top View) and Logic Diagram

Table 3. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

75 kW

Internal Input Pullup Resistor

37.5 kW

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 200 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Pb Pkg

Pb−Free Pkg

SOIC−16

TSSOP−16

Level 1

Level 1

Level 1

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

210 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.