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CS5422 Datasheet(PDF) 15 Page - ON Semiconductor

Part No. CS5422
Description  Dual Out−of−Phase Synchronous Buck Controller with Current Limit
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS5422 Datasheet(HTML) 15 Page - ON Semiconductor

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15
internal slope compensation is insufficient, the performance
of the CS5422−based regulator can be improved through the
addition of a fixed amount of external slope compensation
at the output of the PWM Error Amplifier (the COMP pin)
during the regulator off−time. Referring to Figure 8, the
amount of voltage ramp at the COMP pin is dependent on the
gate voltage of the lower (synchronous) FET and the value
of resistor divider formed by R1and R2.
VSLOPECOMP + VGATE(L)
R2
R1 ) R2
(1 * e
−t
t )
where:
VSLOPECOMP = amount of slope added;
VGATE(L) = lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = tON or tOFF (switch off−time);
τ = RC constant determined by C1 and the parallel
combination of R1, R2 neglecting the low driver
output impedance.
Figure 10. Small RC Filter Provides the
Proper Voltage Ramp at the Beginning of
Each On−Time Cycle
To Synchronous
FET
C1
R2
R1
CS5422
GATE(L)
COMP
CCOMP
The artificial voltage ramp created by the slope
compensation scheme results in improved control loop
stability provided that the RC filter time constant is smaller
than the off−time cycle duration (time during which the
lower MOSFET is conducting). It is important that the series
combination of R1 and R2 is high enough in resistance to
avoid loading the GATE(L) pin. Also, C1 should be very
small (less than a few nF) to avoid heating the part.
EMI MANAGEMENT
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
LAYOUT GUIDELINES
When laying out the CPU buck regulator on a printed
circuit board, the following checklist should be used to
ensure proper operation of the CS5422.
1. Rapid changes in voltage across parasitic capacitors
and abrupt changes in current in parasitic inductors
are major concerns for a good layout.
2. Keep high currents out of sensitive ground
connections.
3. Avoid ground loops as they pick up noise. Use star or
single point grounding.
4. For high power buck regulators on double−sided
PCB’s a single ground plane (usually the bottom) is
recommended.
5. Even though double sided PCB’s are usually
sufficient for a good layout, four−layer PCB’s are the
optimum approach to reducing susceptibility to
noise. Use the two internal layers as the power and
GND planes, the top layer for power connections and
component vias, and the bottom layers for the noise
sensitive traces.
6. Keep the inductor switching node small by placing
the output inductor, switching and synchronous FETs
close together.
7. The MOSFET gate traces to the IC must be short,
straight, and wide as possible.
8. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
9. Place the switching MOSFET as close to the input
capacitors as possible.
10. Place the output capacitors as close to the load as
possible.
11. Place the COMP capacitor as close as possible to the
COMP pin.
12. Connect the filter components of the following pins:
ROSC, VFB, VOUT, and COMP to the GND pin with a
single trace, and connect this local GND trace to the
output capacitor GND.
13. Place the VCC bypass capacitors as close as possible
to the IC.
14. Place the ROSC resistor as close as possible to the
ROSC pin.
15. Include provisions for 100−100pF capacitor across
each resistor of the feedback network to improve
noise immunity and add COMP.
16. Assign the output with lower duty cycle to channel 2,
which has better noise immunity.


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