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CS5422 Datasheet(PDF) 12 Page  ON Semiconductor 

CS5422 Datasheet(HTML) 12 Page  ON Semiconductor 
12 / 17 page CS5422 http://onsemi.com 12 The voltage change during the load current transient is: DVOUT + DIOUT ESL Dt ) ESR ) tTR COUT where: ΔIOUT / Δt = load current slew rate; ΔIOUT = load transient; Δt = load transient duration time; ESL = Maximum allowable ESL including capacitors, circuit traces, and vias; ESR = Maximum allowable ESR including capacitors and circuit traces; tTR = output voltage transient response time. The designer has to independently assign values for the change in output voltage due to ESR, ESL, and output capacitor discharging or charging. Empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor ESR. The maximum allowable ESR can then be determined according to the formula: ESRMAX + DVESR DIOUT where: ΔVESR = change in output voltage due to ESR (assigned by the designer) Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the formula: Number of capacitors + ESRCAP ESRMAX where: ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheet). ESRMAX = maximum allowable ESR. The actual output voltage deviation due to ESR can then be verified and compared to the value assigned by the designer: DVESR + DIOUT ESRMAX Similarly, the maximum allowable ESL is calculated from the following formula: ESLMAX + D VESL Dt DI Selection of the Input Inductor A common requirement is that the buck controller must not disturb the input voltage. One method of achieving this is by using an input inductor and a bypass capacitor. The input inductor isolates the supply from the noise generated in the switching portion of the buck regulator and also limits the inrush current into the input capacitors upon power up. The inductor’s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case is when the load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. The inductor successfully blocks the ripple current while placing the transient current requirements on the input bypass capacitor bank, which has to initially support the sudden load change. The minimum inductance value for the input inductor is therefore: LIN + DV (dI dt)MAX where: LIN = input inductor value; ΔV = voltage seen by the input inductor during a full load swing; (dI/dt)MAX = maximum allowable input current slew rate. The designer must select the LC filter pole frequency so that at least 40 dB attenuation is obtained at the regulator switching frequency. The LC filter is a double−pole network with a slope of −2.0, a roll−off rate of −40 dB/dec, and a corner frequency: fC + 1 2p LC where: L = input inductor; C = input capacitor(s). SELECTION OF THE POWER FET FET Basics The use of the MOSFET as a power switch is propelled by two reasons: 1) Its very high input impedance; and 2) Its very fast switching times. The electrical characteristics of a MOSFET are considered to be those of a perfect switch. Control and drive circuitry power is therefore reduced. Because the input impedance is so high, it is voltage driven. The input of the MOSFET acts as if it were a small capacitor, which the driving circuit must charge at turn on. The lower the drive impedance, the higher the rate of rise of VGS, and the faster the turn−on time. Power dissipation in the switching MOSFET consists of 1) conduction losses, 2) leakage losses, 3) turn−on switching losses, 4) turn−off switching losses, and 5) gate−transitions losses. The latter three losses are proportional to frequency. The most important aspect of FET performance is the Static Drain−To−Source On−Resistance (RDS(ON)), which affects regulator efficiency and FET thermal management requirements. The On−Resistance determines the amount of current a FET can handle without excessive power dissipation that may cause overheating and potentially catastrophic failure. As the drain current rises, especially above the continuous rating, the On−Resistance also increases. Its positive temperature coefficient is between +0.6%/°C and +0.85%/°C. The higher the On−Resistance the larger the conduction loss is. Additionally, the FET gate charge should be low in order to minimize switching losses and reduce power dissipation. 
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