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CS5421 Datasheet(PDF) 4 Page - ON Semiconductor

Part No. CS5421
Description  Dual Out−of−Phase Synchronous Buck Controller with Remote Sense
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS5421 Datasheet(HTML) 4 Page - ON Semiconductor

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CS5421
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ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 μF,
10.8 V < VCC < 13.2 V; CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF, unless otherwise specified.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
PWM Comparator
Transient Response
COMP1,2 = 1.0 V, VFB1(2) = VFFB1(2) = 0 to 1.2 V
150
300
ns
PWM Comparator Offset
VFFB1(2) = 0 V; Increase COMP1,2 until
GATE(H)1,2 starts switching
0.30
0.45
0.60
V
Artificial Ramp
Duty cycle = 50%, Note 3
40
70
100
mV
VFFB1(2) Bias Current
VFFB1(2) = 0 V
0.4
1.5
μA
VFFB1(2) Input Range
0.0
1.1
V
Minimum Pulse Width
300
ns
Oscillator
Switching Frequency
ROSC = 61.9 k; Measure GATE(H)2, Note 3
112
150
188
kHz
Switching Frequency
ROSC = 30.9 k; Measure GATE(H)2
224
300
376
kHz
Switching Frequency
ROSC = 11.8 k; Measure GATE(H)2, Note 3
600
750
900
kHz
ROSC Voltage
ROSC = 30.9 k, Note 3
0.970
1.000
1.030
V
Phase Difference
180
°
Supply Currents
VCC Current
COMP1,2 = 0 V (No Switching)
16
22
mA
SGND Current
75
150
225
μA
Undervoltage Lockout
Start Threshold
GATE(H) Switching; COMP1,2 charging
7.8
8.6
9.6
V
Stop Threshold
GATE(H) not switching; COMP1,2 discharging
7.0
7.8
8.6
V
Hysteresis
Start−Stop
0.5
0.8
1.5
V
3. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16 Lead SO Narrow
1
GATE(H)1
High Side Switch FET driver pin for the channel 1 FET.
2
GATE(L)1
Low Side Synchronous FET driver pin for the channel 1 FET.
3
PGND1
High Current ground for the GATE(H)1 and GATE(L)1 pins.
4
LGND
Logic ground. All control circuits are referenced to this pin. IC
substrate connection.
5
SGND
Ground sense for the internal reference.
6
VFFB1
Input for the channel 1 PWM comparator.
7
VFB1
Error amplifier inverting input for channel 1.
8
COMP1
Channel 1 Error Amp output. PWM Comparator reference
input. A capacitor to LGND provides Error Amp compensa-
tion. The same capacitor provides Soft Start timing for chan-
nel 1. This pin also disables the channel 1 output when
pulled below 0.3 V.
9
COMP2
Channel 2 Error Amp output. PWM Comparator reference
input. A capacitor to LGND provides Error Amp compensa-
tion and Soft Start timing for channel 2. Channel 2 output is
disabled when this pin is pulled below 0.3 V.


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