Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ADM1192 Datasheet(PDF) 4 Page - Analog Devices

Part No. ADM1192
Description  Digital Power Monitor with Clear Pin and ALERT Output
Download  20 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

ADM1192 Datasheet(HTML) 4 Page - Analog Devices

 
Zoom Inzoom in Zoom Outzoom out
 4 / 20 page
background image
ADM1192
Rev. 0 | Page 4 of 20
Parameter
Min
Typ
Max
Unit
Conditions
SETV PIN
Overcurrent Trip Threshold
98
100
102
mV
VSETV = 1.8 V
49.5
50
50.5
mV
VSETV = 0.9 V
Overcurrent Trip, Gain {VSETV/(VVCC − VSENSE)}
18
VSETV = 0.9 V to 1.9 V
Input Current, ISETVLEAK
−1
+1
μA
VSETV = 0.9 V to 1.9 V
Glitch Filter, tSETVGLITCH
3
μs
TIMER PIN
Pull-Up Current (Overcurrent Fault), ITIMERUPOC
−46
−62
−78
μA
(18.125 × VSENSE) > VSETV, VTIMER = 1 V
Pull-Down Current, ITIMERDN
100
μA
Normal Operation, VTIMER = 1 V
Pin Threshold High, VTIMERH
1.275
1.3
1.325
V
TIMER rising
ALERT PIN
Output Low Voltage, VALERTOL
0.05
0.1
V
IALERT = −100 μA
1
1.5
mA
IALERT = −2 mA
Input Current, IALERT
−1
+1
μA
VALERT = VCC; ALERT asserted
ADR PIN
Set Address to 00, VADRLOWV
0
0.8
V
Low state
Set Address to 01, RADRLOWZ
80
120
160
Resistor to ground state, load pin with
specified resistance for 01 decode
Set Address to 10, IADRHIGHZ
−0.3
+0.3
μA
Open state, maximum load allowed on
ADR pin for 10 decode
Set Address to 11, VADRHIGHV
2
5.5
V
High state
Input Current for 00 Decode, IADRLOW
3
6
μA
VADR = 2.0 V to 5.5 V
Input Current for 11 Decode, IADRHIGH
−40
−25
μA
VADR = 0 V to 0.8 V
I2C TIMING
Low Level Input Voltage, VIL
0.3 VBUS
V
High Level Input Voltage, VIH
0.7 VBUS
V
Low Level Output Voltage on SDA, VOL
0.4
V
IOL = 3 mA
Output Fall Time on SDA from VIHMIN to VILMAX
20 +
0.1 CB
250
ns
CB = bus capacitance from SDA to GND
Maximum Width of Spikes Suppressed by Input
Filtering on SDA and SCL Pins
50
250
ns
Input Current, II, on SDA/SCL When not Driving
Out a Logic Low
−10
+10
μA
Input Capacitance on SDA/SCL
5
pF
SCL Clock Frequency, fSCL
400
kHz
Low Period of the SCL Clock
600
ns
High Period of the SCL Clock
1300
ns
Setup Time for Repeated Start Condition, tSU;STA
600
ns
SDA Output Data Hold Time, tHD;DAT
100
900
ns
Setup Time for a Stop Condition, tSU;STO
600
ns
Bus Free Time Between a Stop and a Start
Condition, tBUF
1300
ns
Capacitive Load for Each Bus Line
400
pF
1 Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC
error, and error in ADC full-scale code conversion factor.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn