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CS5165A Datasheet(PDF) 3 Page - ON Semiconductor

Part No. CS5165A
Description  5−Bit Synchronous CPU Buck Controller
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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CS5165A Datasheet(HTML) 3 Page - ON Semiconductor

 
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CS5165A
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (0
°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC < 14 V; 2.8 DAC Code:
(VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0); CGATE(H) and CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 mF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
VCC Supply Current
Operating
1.0 V < VFB < VDAC (max on−time)
No Loads on GATE(H) and GATE(L)
12
20
mA
Sleep Mode
ENABLE = 0 V
300
600
mA
VCC Monitor
Start Threshold
GATE(H) switching
3.75
3.95
4.15
V
Stop Threshold
GATE(H) not switching
3.65
3.87
4.05
V
Hysteresis
Start−Stop
80
mV
Error Amplifier
VFB Bias Current
VFB = 0 V
0.1
1.0
mA
COMP Source Current
COMP = 1.2 V to 3.6 V; VFB = 2.7 V
15
30
60
mA
COMP CLAMP Voltage
VFB = 2.7 V, Adjust COMP voltage for Comp current = 50 mA
0.85
1.0
1.15
V
COMP Clamp Current
COMP = 0 V
0.4
1.0
1.6
mA
COMP Sink Current
VCOMP = 1.2 V; VFB = 3.0 V; VSS > 2.5 V
180
400
800
mA
Open Loop Gain
(Note 2)
50
60
dB
Unity Gain Bandwidth
(Note 2)
0.5
2.0
MHz
PSRR @ 1.0 kHz
(Note 2)
60
85
dB
GATE(H) and GATE(L)
High Voltage at 100 mA
Measure VCC − GATE
1.2
2.0
V
Low Voltage at 100 mA
Measure GATE
1.0
1.5
V
Rise Time
1.6 V < GATE < (VCC − 2.5 V)
40
80
ns
Fall Time
(VCC − 2.5 V) > GATE > 1.6 V
40
80
ns
GATE(H) to GATE(L) Delay
GATE(H) < 2.0 V; GATE(L) > 2.0 V
30
65
100
ns
GATE(L) to GATE(H) Delay
GATE(L) < 2.0 V; GATE(H) > 2.0 V
30
65
100
ns
GATE pulldown
Resistor to PGND, (Note 2)
20
50
115
k
W
Fault Protection
SS Charge Time
VFB = 0 V
1.6
3.3
5.0
ms
SS Pulse Period
VFB = 0 V
25
100
200
ms
SS Duty Cycle
(Charge Time/Period)
× 100
1.0
3.3
6.0
%
SS COMP Clamp Voltage
VFB = 2.7 V; VSS = 0 V
0.50
0.95
1.10
V
VFB Low Comparator
Increase VFB till no SS pulsing and normal Off−time
0.9
1.0
1.1
V
PWM Comparator
Transient Response
VFB = 1.2 to 5.0 V. 500 ns after GATE(H)
(after Blanking time) to GATE(H) = (VCC −1.0 V) to 1.0 V
130
180
ns
Minimum Pulse Width
(Blanking Time)
Drive VFB. 1.2 to 5.0 V upon GATE(H) rising edge
(> VCC − 1.0 V), measure GATE(H) pulse width
50
150
250
ns
COFF
Normal Off−Time
VFB = 2.7 V
1.0
1.6
2.3
ms
Extended Off−Time
VSS = VFB = 0 V
5.0
8.0
12.0
ms
Time−Out Timer
Time−Out Time
VFB = 2.7 V, Measure GATE(H) Pulse Width
10
30
50
ms
Fault Duty Cycle
VFB = 0V
30
50
70
%
Enable Input
ENABLE Threshold
GATE(H) Switching
0.8
1.15
1.30
V
Shutdown delay (Note 3)
ENABLE−to−GATE(H) < 2.0 V
3.0
ms
2. Guaranteed by design, not 100% tested in production.


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