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CS5165A Datasheet(PDF) 12 Page - ON Semiconductor

Part No. CS5165A
Description  5−Bit Synchronous CPU Buck Controller
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS5165A Datasheet(HTML) 12 Page - ON Semiconductor

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CS5165A
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12
remain in this state until the overvoltage condition ceases or the
input voltage is pulled low. The bottom FET and board trace
must be properly designed to implement the OVP function.If
a dedicated OVP output is required, it can be implemented
using the circuit in Figure 22. In this figure the OVP signal will
go high (overvoltage condition), if the output voltage (VCORE)
exceeds 20% of the voltage set by the particular DAC code and
provided that PWRGD is low. It is also required that the
overvoltage condition be present for at least the PWRGD delay
time for the OVP signal to be activated. The resistor values
shown in Figure 22 are for VDAC = +2.8 V (DAC = 10111).
The VOVP (overvoltage trip−point) can be set using the
following equation:
VOVP + VBEQ3 1 )
R2
R1
Figure 20. OVP Response to an Input−to−Output
Short Circuit by Immediately Providing 0% Duty
Cycle, Crow−Barring the Input Voltage to Ground
M 10.0
ms
Trace 1− Regulator Output Voltage (1.0 V/div.)
Trace 2− Inductor Switching Node 5.0 V/div.)
Trace 4− 5.0 V from PC Power Supply (5.0 V/div.)
Figure 21. OVP Response to an Input−to−Output Short
Circuit by Pulling the Input Voltage to Ground
M 5.00 ms
Trace 1− Regulator Output Voltage (1.0 V/div.)
Trace 4− 5.0 V from PC Power Supply (2.0 V/div.)
Figure 22. Circuit To Implement A Dedicated OVP
Output Using The CS5165A
CS5165A
PWRGD
+5.0 V
10 k
Q1
2N3906
2N3904
Q2
20 k
5.0 k
+5.0 V
10 k
10 K
OVP
Q3
2N3906
56 k
15 k
VCORE
R1
R2
Output Enable Circuit
The Enable pin (pin 8) is used to enable or disable the
regulator output voltage, and is consistent with TTL DC
specifications. It is internally pulled−up. If pulled low (below
0.8 V), the output voltage is disabled. At the same time the
Power Good and Soft−Start pins are pulled low, so that when
normal operation resumes power−up of the CS5165A goes
through the Soft−Start sequence. Upon pulling the Enable pin
low, the internal IC bias is completely shut off, resulting in
total shutdown of the Controller IC.
Power Good Circuit
The Power Good pin (pin 13) is an open−collector signal
consistent with TTL DC specifications. It is externally
pulled−up, and is pulled low (below 0.3 V) when the regulator
output voltage typically exceeds
± 8.5% of the nominal output
voltage. Maximum output voltage deviation before Power
Good is pulled low is
± 12%.
Figure 23. PWRGD Signal Becomes Logic High as
VOUT Enters −8.5% of Lower PWRGD Threshold,
VOUT = +2.84 V (DAC = 10111)
Trace 4− VOUT (1.0 V/div.)
Trace 2− PWRGD (2.0 V/div.)


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