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CS5160 Datasheet(PDF) 13 Page - ON Semiconductor

Part No. CS5160
Description  CPU 5−Bit Synchronous Buck Controller
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS5160 Datasheet(HTML) 13 Page - ON Semiconductor

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CS5160
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The circuit that implements this function is shown in
Figure 19.
Figure 19. Small RC Filter Provides the
Proper Voltage Ramp at the Beginning of
each On−Time Cycle
To Synchronous
FET
16
VOUT
12
C1
R2
R1
CS5160
GATE(L)
COMP
CCOMP
The ramp waveform is generated through a small RC filter
that provides the proper voltage ramp at the beginning of
each on−time cycle. The resistors R1 and R2 in the circuit of
Figure 14 form a voltage divider from the GATE(L) output,
superimposing a small artificial ramp on the output of the
error amplifier. It is important that the series combination
R1/R2 is high enough in resistance not to load down and
negatively affect the slew rate on the GATE(L) pin.
Selecting External Components
The CS5160 can be used with a wide range of external
power components to optimize the cost and performance of
a particular design. The following information can be used
as general guidelines to assist in their selection.
NFET Power Transistors
Both logic level and standard MOSFETs can be used. The
reference designs derive gate drive from the 12 V supply
which is generally available in most computer systems and
utilize logic level MOSFETs. Multiple MOSFETs may be
paralleled to reduce losses and improve efficiency and
thermal management.
Voltage applied to the MOSFET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the MOSFET
gates will be driven rail to rail due to overshoot caused by the
capacitive load they present to the controller IC. For the
typical application where VCC1 = VCC2 = 12 V and 5.0 V is
used as the source for the regulator output current, the
following gate drive is provided;
VGATE(H) + 12 V * 5.0 V + 7.0 V, VGATE(L) + 12 V
(see Figure 20.)
Figure 20. CS5160 Gate Drive Waveforms Depicting
Rail to Rail Swing
M 1.00 μs
Math 1 = VGATE(H) − 5.0 VIN
Trace 3 = VGATE(H) (10 V/div.)
Trace 4 = VGATE(L) (10 V/div.)
Trace 2= Inductor Switching Nodes (5.0 V/div.)
The most important aspect of MOSFET performance is
RDSON, which effects regulator efficiency and MOSFET
thermal management requirements.
The power dissipated by the MOSFETs may be estimated
as follows;
Switching MOSFET:
Power + ILOAD2
RDSON
duty cycle
Synchronous MOSFET:
Power + ILOAD2
RDSON
(1 * duty cycle)
Duty Cycle =
VOUT ) (ILOAD
RDSON OF SYNCH FET)
VIN)(ILOAD
RDSON OF SYNCH FET)
* (ILOAD
RDSON OF SWITCH FET)
Off Time Capacitor (COFF)
The COFF timing capacitor sets the regulator off time:
TOFF + COFF
4848.5
The preceding equations for duty cycle can also be used
to calculate the regulator switching frequency and select the
COFF timing capacitor:
COFF +
Perioid
(1 * duty cycle)
4848.5
where:
Period +
1
switching frequency


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